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Core Opimized

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This commit is contained in:
CGH0S7
2024-12-28 08:39:07 +08:00
parent 7d9846b4a6
commit 66cda81233
56 changed files with 591 additions and 154 deletions
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2
.gitignore vendored
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@ -6,7 +6,7 @@
.bloop
.scalafmt.conf
*.code-workspace
target
target/*
.vscode
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml

22
Top.sv
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@ -107,10 +107,11 @@ module Core(
automatic logic _csignals_T_33;
automatic logic _csignals_T_35;
automatic logic _csignals_T_37;
automatic logic _csignals_T_39;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic [1:0] csignals_1;
automatic logic [2:0] _csignals_T_90;
automatic logic [2:0] _csignals_T_95;
automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
automatic logic [62:0] _exe_alu_out_T_8 =
{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
@ -148,14 +149,17 @@ module Core(
_csignals_T_33 = id_inst == 32'hC000000;
_csignals_T_35 = _GEN_0 == 20'h8;
_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
_csignals_T_39 = id_inst == 32'h0;
_GEN_2 = _csignals_T_29 | _csignals_T_31;
_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
? 2'h0
: _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
_csignals_T_90 =
: _csignals_T_33
? 2'h1
: _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
_csignals_T_95 =
_csignals_T_5
? 3'h1
: _csignals_T_7
@ -168,7 +172,9 @@ module Core(
? 3'h1
: _csignals_T_33
? 3'h4
: _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1};
: _csignals_T_35
? 3'h0
: _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
exe_alu_out =
exe_reg_exe_fun == 5'hE
? exe_reg_op1_data
@ -212,13 +218,13 @@ module Core(
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
if (_csignals_T_90 == 3'h5)
if (_csignals_T_95 == 3'h5)
exe_reg_op2_data <= {id_inst[15:0], 16'h0};
else if (_csignals_T_90 == 3'h4)
else if (_csignals_T_95 == 3'h4)
exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
else if (_csignals_T_90 == 3'h3 | _csignals_T_90 == 3'h2)
else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
else if (_csignals_T_90 != 3'h1 | _id_rs2_data_T)
else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
exe_reg_op2_data <= 32'h0;
else
exe_reg_op2_data <= _id_rs2_data_T_8;

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// Generated by CIRCT firtool-1.62.0
// VCS coverage exclude_file
module regfile_32x32(
input [4:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [4:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [4:0] W0_addr,
input W0_en,
W0_clk,
input [31:0] W0_data
);
reg [31:0] Memory[0:31];
reg _R0_en_d0;
reg [4:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
reg _R1_en_d0;
reg [4:0] _R1_addr_d0;
always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
endmodule
module Core(
input clock,
reset,
output [31:0] io_imem_addr,
input [31:0] io_imem_inst,
output [31:0] io_dmem_addr,
input [31:0] io_dmem_rdata,
output io_dmem_wen,
output [31:0] io_dmem_wdata,
output io_exit
);
wire [31:0] _regfile_ext_R0_data;
wire [31:0] _regfile_ext_R1_data;
reg [31:0] id_reg_pc;
reg [31:0] id_reg_inst;
reg [31:0] exe_reg_pc;
reg [4:0] exe_reg_wb_addr;
reg [31:0] exe_reg_op1_data;
reg [31:0] exe_reg_op2_data;
reg [31:0] exe_reg_rs2_data;
reg [4:0] exe_reg_exe_fun;
reg [1:0] exe_reg_mem_wen;
reg [1:0] exe_reg_rf_wen;
reg [2:0] exe_reg_wb_sel;
reg [31:0] exe_reg_imm_b_sext;
reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_alu_out;
reg [31:0] mem_reg_rs2_data;
reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel;
reg [1:0] mem_reg_mem_wen;
reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc;
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
wire exe_br_flg =
exe_reg_exe_fun == 5'hC
? exe_reg_op1_data != exe_reg_op2_data
: exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
wire exe_jmp_flg = exe_reg_wb_sel == 3'h3;
always @(posedge clock) begin
automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg;
automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
automatic logic stall_flg;
automatic logic [31:0] id_inst;
automatic logic _id_rs2_data_T_2;
automatic logic _id_rs2_data_T;
automatic logic [31:0] _id_rs2_data_T_8;
automatic logic [16:0] _GEN;
automatic logic _csignals_T_5;
automatic logic [19:0] _GEN_0;
automatic logic _csignals_T_7;
automatic logic _csignals_T_9;
automatic logic _csignals_T_11;
automatic logic _csignals_T_13;
automatic logic _csignals_T_15;
automatic logic _csignals_T_17;
automatic logic _csignals_T_19;
automatic logic [16:0] _GEN_1;
automatic logic _csignals_T_21;
automatic logic _csignals_T_23;
automatic logic _csignals_T_25;
automatic logic _csignals_T_27;
automatic logic _csignals_T_29;
automatic logic _csignals_T_31;
automatic logic _csignals_T_33;
automatic logic _csignals_T_35;
automatic logic _csignals_T_37;
automatic logic _csignals_T_39;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic [1:0] csignals_1;
automatic logic [2:0] _csignals_T_95;
automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
automatic logic [62:0] _exe_alu_out_T_8 =
{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
automatic logic [31:0] exe_alu_out;
stall_flg =
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
_id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
_id_rs2_data_T_8 =
id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_reg_alu_out
: id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data
: _regfile_ext_R0_data;
_GEN = {id_inst[31:26], id_inst[10:0]};
_csignals_T_5 = _GEN == 17'h20;
_GEN_0 = {id_inst[31:28], id_inst[15:0]};
_csignals_T_7 = _GEN_0 == 20'h80000;
_csignals_T_9 = _GEN == 17'h22;
_csignals_T_11 = _GEN == 17'h24;
_csignals_T_13 = _GEN == 17'h25;
_csignals_T_15 = _GEN == 17'h26;
_csignals_T_17 = _GEN_0 == 20'hC0000;
_csignals_T_19 = _GEN_0 == 20'hD0000;
_GEN_1 = {id_inst[30:20], id_inst[5:0]};
_csignals_T_21 = _GEN_1 == 17'h0;
_csignals_T_23 = _GEN_1 == 17'h2;
_csignals_T_25 = _GEN_1 == 17'h3;
_csignals_T_27 = _GEN == 17'h2A;
_csignals_T_29 = _GEN_0 == 20'h40000;
_csignals_T_31 = _GEN_0 == 20'h50000;
_csignals_T_33 = id_inst == 32'hC000000;
_csignals_T_35 = _GEN_0 == 20'h8;
_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
_csignals_T_39 = id_inst == 32'h0;
_GEN_2 = _csignals_T_29 | _csignals_T_31;
_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
? 2'h0
: _csignals_T_33
? 2'h1
: _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
_csignals_T_95 =
_csignals_T_5
? 3'h1
: _csignals_T_7
? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_3
? 3'h1
: _csignals_T_33
? 3'h4
: _csignals_T_35
? 3'h0
: _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
exe_alu_out =
exe_reg_exe_fun == 5'hE
? exe_reg_op1_data
: exe_reg_exe_fun == 5'h9
? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
: exe_reg_exe_fun == 5'h8
? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
: exe_reg_exe_fun == 5'h7
? exe_reg_op1_data >> _GEN_4
: exe_reg_exe_fun == 5'h6
? _exe_alu_out_T_8[31:0]
: exe_reg_exe_fun == 5'h5
? exe_reg_op1_data ^ exe_reg_op2_data
: exe_reg_exe_fun == 5'h4
? exe_reg_op1_data | exe_reg_op2_data
: exe_reg_exe_fun == 5'h3
? exe_reg_op1_data & exe_reg_op2_data
: exe_reg_exe_fun == 5'h2
? exe_reg_op1_data - exe_reg_op2_data
: exe_reg_exe_fun == 5'h1
? exe_reg_op1_data + exe_reg_op2_data
: 32'h0;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
id_reg_inst <= 32'h0;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_reg_inst[15:11];
if (csignals_1 == 2'h0)
exe_reg_op1_data <=
id_reg_inst[25:21] == 5'h0
? 32'h0
: id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_reg_alu_out
: id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data
: _regfile_ext_R1_data;
else if (csignals_1 == 2'h1)
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
if (_csignals_T_95 == 3'h5)
exe_reg_op2_data <= {id_inst[15:0], 16'h0};
else if (_csignals_T_95 == 3'h4)
exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
exe_reg_op2_data <= 32'h0;
else
exe_reg_op2_data <= _id_rs2_data_T_8;
exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
if (_csignals_T_5 | _csignals_T_7)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2;
else if (_csignals_T_11)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_13)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_15)
exe_reg_exe_fun <= 5'h5;
else if (_csignals_T_17)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_19)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_21)
exe_reg_exe_fun <= 5'h6;
else if (_csignals_T_23)
exe_reg_exe_fun <= 5'h7;
else if (_csignals_T_25)
exe_reg_exe_fun <= 5'h8;
else if (_csignals_T_27)
exe_reg_exe_fun <= 5'h9;
else if (_csignals_T_29)
exe_reg_exe_fun <= 5'hB;
else if (_csignals_T_31)
exe_reg_exe_fun <= 5'hC;
else if (_csignals_T_33)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_35)
exe_reg_exe_fun <= 5'hE;
else
exe_reg_exe_fun <= {4'h0, _csignals_T_37};
exe_reg_mem_wen <= 2'h0;
if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1;
end
else if (_GEN_2) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else if (_csignals_T_33) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h3;
end
else if (_csignals_T_35) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else begin
exe_reg_rf_wen <= {1'h0, _csignals_T_37};
exe_reg_wb_sel <= {2'h0, _csignals_T_37};
end
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_alu_out <= exe_alu_out;
mem_reg_rs2_data <= exe_reg_rs2_data;
mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_mem_wen <= exe_reg_mem_wen;
wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <=
mem_reg_wb_sel == 3'h3
? mem_reg_pc + 32'h4
: mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
if (reset)
if_reg_pc <= 32'h0;
else if (exe_br_flg)
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
else if (exe_jmp_flg)
if_reg_pc <= exe_alu_out;
else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4;
end // always @(posedge)
regfile_32x32 regfile_ext (
.R0_addr (id_reg_inst[20:16]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.R1_addr (id_reg_inst[25:21]),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_regfile_ext_R1_data),
.W0_addr (wb_reg_wb_addr),
.W0_en (_id_rs2_data_T_5),
.W0_clk (clock),
.W0_data (wb_reg_wb_data)
);
assign io_imem_addr = if_reg_pc;
assign io_dmem_addr = mem_reg_alu_out;
assign io_dmem_wen = mem_reg_mem_wen[0];
assign io_dmem_wdata = mem_reg_rs2_data;
assign io_exit = id_reg_inst == 32'hC0000000;
endmodule
// VCS coverage exclude_file
module mem_512x32(
input [8:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [8:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [8:0] W0_addr,
input W0_en,
W0_clk,
input [31:0] W0_data
);
reg [31:0] Memory[0:511];
reg _R0_en_d0;
reg [8:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
reg _R1_en_d0;
reg [8:0] _R1_addr_d0;
always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
initial
$readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
endmodule
module Memory(
input clock,
input [31:0] io_imem_addr,
output [31:0] io_imem_inst,
input [31:0] io_dmem_addr,
output [31:0] io_dmem_rdata,
input io_dmem_wen,
input [31:0] io_dmem_wdata
);
mem_512x32 mem_ext (
.R0_addr (io_imem_addr[10:2]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_imem_inst),
.R1_addr (io_dmem_addr[10:2]),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (io_dmem_rdata),
.W0_addr (io_dmem_addr[10:2]),
.W0_en (io_dmem_wen),
.W0_clk (clock),
.W0_data (io_dmem_wdata)
);
endmodule
module TopOrigin(
input clock,
reset,
output io_exit
);
wire [31:0] _memory_io_imem_inst;
wire [31:0] _memory_io_dmem_rdata;
wire [31:0] _core_io_imem_addr;
wire [31:0] _core_io_dmem_addr;
wire _core_io_dmem_wen;
wire [31:0] _core_io_dmem_wdata;
Core core (
.clock (clock),
.reset (reset),
.io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata),
.io_exit (io_exit)
);
Memory memory (
.clock (clock),
.io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata)
);
endmodule

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sbt.internal.DslEntry

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sbt.internal.DslEntry

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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

2
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

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/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

6
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[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak

2
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/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

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/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

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project/project/target/config-classes/$c1a540d1f89b99cfe151.cache Executable file
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sbt.internal.DslEntry

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project/project/target/config-classes/$ce6b00de31b68d292230.cache Executable file
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sbt.internal.DslEntry

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project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

2
project/project/target/streams/compile/_global/_global/compileOutputs/previous
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

2
project/project/target/streams/compile/bloopGenerate/_global/streams/out
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[debug] [micore-build-build] Classpath dependencies List()
[debug] [micore-build-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build-build' to '/home/gh0s7/nfs/project/micore/project/project/.bloop/micore-build-build.json'
[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'
[success] Generated .bloop/micore-build-build.json

2
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/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes

6
project/project/target/streams/compile/incOptions/_global/streams/out
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@ -1,5 +1,5 @@
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak

2
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/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes

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/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

2
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/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
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1
project/target/config-classes/$0dd3447347b5224615e5.cache Executable file
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sbt.internal.DslEntry

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project/target/config-classes/$6becda8e2cd53152091b.cache Executable file
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root

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project/target/config-classes/$afff5d25069ab86e2b89.cache Executable file
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sbt.internal.DslEntry

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project/target/config-classes/$cc949d4e621f82777efc.cache Executable file
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sbt.internal.DslEntry

2
project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

2
project/target/streams/compile/_global/_global/compileOutputs/previous
View File

@ -1 +1 @@
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

2
project/target/streams/compile/bloopGenerate/_global/streams/out
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@ -1,4 +1,4 @@
[debug] [micore-build] Classpath dependencies List()
[debug] [micore-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build' to '/home/gh0s7/nfs/project/micore/project/.bloop/micore-build.json'
[debug] Bloop wrote the configuration of project 'micore-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/.bloop/micore-build.json'
[success] Generated .bloop/micore-build.json

2
project/target/streams/compile/exportedProducts/_global/streams/export
View File

@ -1 +1 @@
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes

6
project/target/streams/compile/incOptions/_global/streams/out
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@ -1,5 +1,5 @@
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak

2
project/target/streams/runtime/dependencyClasspath/_global/streams/export
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@ -1 +1 @@
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

2
project/target/streams/runtime/exportedProducts/_global/streams/export
View File

@ -1 +1 @@
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes

2
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@ -1 +1 @@
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

2
project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
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@ -1 +1 @@
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes

2
src/main/scala/common/Instructions.scala
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@ -44,4 +44,6 @@ object Instructions {
// * 立即数加载
val LUI = BitPat("b00111100000????????????0000000000") // lui rt, immediate
val NOP = BitPat("b000000000000000000000000000000000") // nop
}

15
src/main/scala/micore/Core.scala
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@ -55,8 +55,8 @@ class Core extends Module {
io.imem.addr := if_reg_pc
val if_inst = io.imem.inst
val stall_flg = Wire(Bool())
val exe_br_flg = Wire(Bool())
val stall_flg = Wire(Bool())
val exe_br_flg = Wire(Bool())
val exe_br_target = Wire(UInt(WORD_LEN.W))
val exe_jmp_flg = Wire(Bool())
val exe_alu_out = Wire(UInt(WORD_LEN.W))
@ -94,7 +94,8 @@ class Core extends Module {
(exe_reg.rf_wen === REN_S) && (id_rs2_addr =/= 0.U) && (id_rs2_addr === exe_reg.wb_addr)
stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg.inst)
val id_inst =
Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg.inst)
val id_rs1_data = Mux(
id_rs1_addr === 0.U,
@ -150,11 +151,13 @@ class Core extends Module {
BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X),
LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU)
LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU),
NOP -> List(ALU_X, OP1_X, OP2_X, MEN_X, REN_X, WB_X)
)
)
val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = csignals
val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil =
csignals
val id_op1_data = Mux(
id_op1_sel === OP1_RS1,
@ -195,7 +198,7 @@ class Core extends Module {
ALU_ADD -> (exe_reg.op1_data + exe_reg.op2_data),
ALU_SUB -> (exe_reg.op1_data - exe_reg.op2_data),
ALU_AND -> (exe_reg.op1_data & exe_reg.op2_data),
ALU_OR -> (exe_reg.op1_data | exe_reg.op2_data),
ALU_OR -> (exe_reg.op1_data | exe_reg.op2_data),
ALU_XOR -> (exe_reg.op1_data ^ exe_reg.op2_data),
ALU_SLL -> (exe_reg.op1_data << exe_reg.op2_data(4, 0))(31, 0),
ALU_SRL -> (exe_reg.op1_data >> exe_reg.op2_data(4, 0)).asUInt,

10
src/main/scala/micore/Top.scala
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@ -5,7 +5,7 @@ import chisel3._
import _root_.circt.stage.ChiselStage
import common.Consts._
class Top extends Module {
class TopOrigin extends Module {
val io = IO(new Bundle {
val exit = Output(Bool())
})
@ -20,11 +20,11 @@ class Top extends Module {
/** Generate Verilog sources and save it in file
*/
object Top extends App {
object TopOrigin extends App {
ChiselStage.emitSystemVerilogFile(
new Top,
firtoolOpts = Array(
"--disable-all-randomization",
new TopOrigin,
firtoolOpts = Array(
"--disable-all-randomization",
"--strip-debug-info",
"--O=release",
"--mlir-timing"

BIN
target/scala-2.13/-name-_2.13-0.1.0.jar Normal file → Executable file
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2
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@ -1 +1 @@
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$4.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$2.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$5.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$3.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]

2
target/streams/compile/_global/_global/discoveredMainClasses/data
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@ -1 +1 @@
["micore.Top"]
["micore.TopOrigin"]

4
target/streams/compile/compile/_global/streams/out
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@ -0,0 +1,4 @@
[error] /run/media/gh0s7/Data/project/ddca2024/micore/src/main/scala/micore/Top.scala:25:9: not found: type TopOrigin
[error]  new TopOrigin,
[error]  ^
[error] one error found

47
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@ -1 +1 @@
/home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar

2
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@ -1 +1 @@
/home/gh0s7/nfs/project/micore/target/scala-2.13/classes
/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes

64
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@ -1,59 +1,19 @@
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/target/scala-2.13/classes.bak
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
[debug] About to delete class files:
[debug]  Core$$anon$1.class
[debug]  Consts$.class
[debug]  Instructions$.class
[debug]  Core$$anon$4.class
[debug]  Core$$anon$2.class
[debug]  Top$.class
[debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class
[debug]  Core.class
[debug]  Core$$anon$5.class
[debug]  Consts.class
[debug]  Core$$anon$3.class
[debug]  DmemPortIo.class
[debug]  Top$delayedInit$body.class
[debug]  Memory.class
[debug]  TopOrigin$delayedInit$body.class
[debug]  TopOrigin.class
[debug]  Top$$anon$1.class
[debug]  Instructions.class
[debug]  TopOrigin$.class
[debug]  Top.class
[debug] We backup class files:
[debug]  Core$$anon$1.class
[debug]  Consts$.class
[debug]  Instructions$.class
[debug]  Core$$anon$4.class
[debug]  Core$$anon$2.class
[debug]  Top$.class
[debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class
[debug]  Core.class
[debug]  Core$$anon$5.class
[debug]  Consts.class
[debug]  Core$$anon$3.class
[debug]  DmemPortIo.class
[debug]  Top$delayedInit$body.class
[debug]  Memory.class
[debug]  TopOrigin$delayedInit$body.class
[debug]  TopOrigin.class
[debug]  Top$$anon$1.class
[debug]  Instructions.class
[debug]  TopOrigin$.class
[debug]  Top.class
[debug] Registering generated classes:
[debug]  Core$$anon$1.class
[debug]  Consts$.class
[debug]  Instructions$.class
[debug]  Core$$anon$4.class
[debug]  Core$$anon$2.class
[debug]  Top$.class
[debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class
[debug]  Core.class
[debug]  Core$$anon$5.class
[debug]  Consts.class
[debug]  Core$$anon$3.class
[debug]  DmemPortIo.class
[debug]  Top$delayedInit$body.class
[debug]  Memory.class
[debug]  Top$$anon$1.class
[debug]  Instructions.class
[debug]  Top.class
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/target/scala-2.13/classes.bak
[debug]  TopOrigin$.class
[debug]  TopOrigin$delayedInit$body.class
[debug]  TopOrigin.class
[debug]  TopOrigin$$anon$1.class
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak

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-1409454022
-153958634

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@ -1,43 +1,43 @@
[debug] Packaging /home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
[debug] Input file mappings:
[debug]  common
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common
[debug]  common/Consts$.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class
[debug]  common/Consts.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class
[debug]  common/Instructions$.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class
[debug]  common/Instructions.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class
[debug]  micore
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore
[debug]  micore/Core.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore
[debug]  micore/Core$$anon$1.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
[debug]  micore/Core$$anon$2.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$2.class
[debug]  micore/Core$$anon$3.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$3.class
[debug]  micore/Core$$anon$4.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$4.class
[debug]  micore/Core$$anon$5.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class
[debug]  micore/ImemPortIo.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$5.class
[debug]  micore/Core.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class
[debug]  micore/DmemPortIo.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class
[debug]  micore/Memory.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class
[debug]  micore/ImemPortIo.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class
[debug]  micore/Memory$$anon$1.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
[debug]  micore/Top.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class
[debug]  micore/Top$.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class
[debug]  micore/Top$$anon$1.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class
[debug]  micore/Top$delayedInit$body.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
[debug]  micore/Memory.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class
[debug]  micore/TopOrigin$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class
[debug]  micore/TopOrigin$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class
[debug]  micore/TopOrigin$delayedInit$body.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class
[debug]  micore/TopOrigin.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class
[debug] Done packaging.

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