59 lines
1.7 KiB
Systemverilog
Executable File
59 lines
1.7 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:25:38
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// Design Name:
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// Module Name: Core
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Top(
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input clock,
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reset,
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output io_exit,
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output [3:0] io_anodes,
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output [6:0] io_segments
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);
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wire [31:0] _memory_io_imem_inst;
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wire [31:0] _memory_io_dmem_rdata;
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wire [31:0] _core_io_imem_addr;
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wire [31:0] _core_io_dmem_addr;
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wire _core_io_dmem_wen;
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wire [31:0] _core_io_dmem_wdata;
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Core core (
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.clock (clock),
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.reset (reset),
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.io_imem_addr (_core_io_imem_addr),
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.io_imem_inst (_memory_io_imem_inst),
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.io_dmem_addr (_core_io_dmem_addr),
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.io_dmem_rdata (_memory_io_dmem_rdata),
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.io_dmem_wen (_core_io_dmem_wen),
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.io_dmem_wdata (_core_io_dmem_wdata),
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.io_anodes (io_anodes),
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.io_segments (io_segments),
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.io_exit (io_exit)
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);
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Memory memory (
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.clock (clock),
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.io_imem_addr (_core_io_imem_addr),
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.io_imem_inst (_memory_io_imem_inst),
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.io_dmem_addr (_core_io_dmem_addr),
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.io_dmem_rdata (_memory_io_dmem_rdata),
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.io_dmem_wen (_core_io_dmem_wen),
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.io_dmem_wdata (_core_io_dmem_wdata)
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);
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endmodule
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