107 lines
3.1 KiB
Systemverilog
Executable File
107 lines
3.1 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:36:13
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// Design Name:
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// Module Name: testbench
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Top_tb;
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reg clock;
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reg reset;
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wire io_exit;
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wire [31:0] if_reg_pc;
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wire [31:0] id_reg_pc;
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wire [31:0] _memory_io_imem_inst;
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wire [31:0] id_inst;
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wire [31:0] id_reg_inst;
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wire [31:0] exe_reg_op1_data;
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wire [31:0] exe_reg_op2_data;
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wire [31:0] exe_alu_out;
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wire [3:0] exe_reg_exe_fun;
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wire exe_br_flg;
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wire stall_flg;
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wire [31:0] mem_reg_alu_out;
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wire [31:0] reg_r8;
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wire [31:0] reg_r10;
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wire [31:0] reg_r16;
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wire [31:0] reg_r18;
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Top uut (
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.clock (clock),
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.reset (reset),
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.io_exit (io_exit)
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);
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assign if_reg_pc = uut.core.if_reg_pc;
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assign id_reg_pc = uut.core.id_reg_pc;
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assign _memory_io_imem_inst = uut.core._memory_io_imem_inst;
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assign id_inst = uut.core.id_inst;
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assign id_reg_inst = uut.core.id_reg_inst;
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assign exe_reg_op1_data = uut.core.exe_reg_op1_data;
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assign exe_reg_op2_data = uut.core.exe_reg_op2_data;
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assign exe_alu_out = uut.core.exe_alu_out;
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assign exe_reg_exe_fun = uut.core.exe_reg_exe_fun;
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assign exe_br_flg = uut.core.exe_br_flg;
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assign stall_flg = uut.core.stall_flg;
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assign mem_reg_alu_out = uut.core.mem_reg_alu_out;
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assign reg_r8 = uut.core.regfile_ext.Memory[8];
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assign reg_r10 = uut.core.regfile_ext.Memory[10];
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assign reg_r16 = uut.core.regfile_ext.Memory[16];
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assign reg_r18 = uut.core.regfile_ext.Memory[18];
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initial begin
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clock = 0;
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forever #5 clock = ~clock; // 10ns
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end
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initial begin
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reset = 1;
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#20;
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reset = 0;
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#1000;
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$finish;
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end
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always @(posedge clock) begin
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if (!reset) begin
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$display("Cycle: %0d", $time / 10);
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$display("if_reg_pc: %h", if_reg_pc);
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$display("id_reg_pc: %h", id_reg_pc);
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$display("if_inst: %h", _memory_io_imem_inst);
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$display("id_inst: %h", id_inst);
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$display("id_reg_inst: %h", id_reg_inst);
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$display("exe_reg_op1_data: %h", exe_reg_op1_data);
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$display("exe_reg_op2_data: %h", exe_reg_op2_data);
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$display("exe_reg_exe_fun: %h", exe_reg_exe_fun);
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$display("exe_alu_out: %h", exe_alu_out);
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$display("exe_br_flg: %h", exe_br_flg);
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$display("stall_flg: %h", stall_flg);
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$display("mem_reg_alu_out: %h", mem_reg_alu_out);
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$display("Registers:");
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$display("R%0d: %h", 8, reg_r8);
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$display("R%0d: %h", 10, reg_r10);
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$display("R%0d: %h", 16, reg_r16);
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$display("R%0d: %h", 18, reg_r18);
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$display("-----------------------------");
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end
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end
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endmodule |