428 lines
18 KiB
Systemverilog
Executable File
428 lines
18 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:25:38
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// Design Name:
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// Module Name: Core
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Core(
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input clock,
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reset,
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output [31:0] io_imem_addr,
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input [31:0] io_imem_inst,
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output [31:0] io_dmem_addr,
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input [31:0] io_dmem_rdata,
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output io_dmem_wen,
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output [31:0] io_dmem_wdata,
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output [3:0] io_anodes,
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output [6:0] io_segments,
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output io_exit
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);
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wire exe_jmp_flg;
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wire exe_br_flg;
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wire [31:0] _regfile_ext_R0_data;
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wire [31:0] _regfile_ext_R1_data;
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reg [31:0] id_reg_pc;
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reg [31:0] id_reg_inst;
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reg [31:0] exe_reg_pc;
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reg [4:0] exe_reg_wb_addr;
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reg [31:0] exe_reg_op1_data;
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reg [31:0] exe_reg_op2_data;
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reg [31:0] exe_reg_rt_data;
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reg [4:0] exe_reg_exe_fun;
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reg [1:0] exe_reg_mem_wen;
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reg [1:0] exe_reg_rf_wen;
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reg [2:0] exe_reg_wb_sel;
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reg [31:0] exe_reg_imm_i_sext;
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reg [31:0] mem_reg_pc;
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reg [4:0] mem_reg_wb_addr;
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reg [31:0] mem_reg_rt_data;
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reg [1:0] mem_reg_mem_wen;
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reg [1:0] mem_reg_rf_wen;
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reg [2:0] mem_reg_wb_sel;
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reg [31:0] mem_reg_alu_out;
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reg [4:0] wb_reg_wb_addr;
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reg [1:0] wb_reg_rf_wen;
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reg [31:0] wb_reg_wb_data;
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reg [31:0] if_reg_pc;
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wire _id_inst_T = exe_br_flg | exe_jmp_flg;
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wire _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
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wire stall_flg =
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_id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
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| _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
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wire _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
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wire _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
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wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
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wire _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
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wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
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wire _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
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wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
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wire _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
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wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
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wire _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
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wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
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wire _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
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wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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wire _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
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wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
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wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
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wire _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
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wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
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wire _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
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wire _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
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wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
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wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
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wire [31:0] exe_alu_out =
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_exe_alu_out_T
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? _exe_alu_out_T_1
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: _exe_alu_out_T_3
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? _exe_alu_out_T_4
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: _exe_alu_out_T_6
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? _exe_alu_out_T_7
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: _exe_alu_out_T_8
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? _exe_alu_out_T_9
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: _exe_alu_out_T_10
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? _exe_alu_out_T_11
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: _exe_alu_out_T_12
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? _exe_alu_out_T_14[31:0]
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: _exe_alu_out_T_16
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? _exe_alu_out_T_18
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: _exe_alu_out_T_19
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? _exe_alu_out_T_22
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: _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
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assign exe_br_flg =
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exe_reg_exe_fun == 5'hB
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? exe_reg_op1_data == exe_reg_op2_data
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: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
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assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
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wire [31:0] mem_wb_data =
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mem_reg_wb_sel == 3'h2
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? io_dmem_rdata
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: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
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always @(posedge clock) begin
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if (reset) begin
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id_reg_pc <= 32'h0;
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id_reg_inst <= 32'h0;
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exe_reg_pc <= 32'h0;
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exe_reg_wb_addr <= 5'h0;
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exe_reg_op1_data <= 32'h0;
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exe_reg_op2_data <= 32'h0;
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exe_reg_rt_data <= 32'h0;
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exe_reg_exe_fun <= 5'h0;
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exe_reg_mem_wen <= 2'h0;
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exe_reg_rf_wen <= 2'h0;
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exe_reg_wb_sel <= 3'h0;
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exe_reg_imm_i_sext <= 32'h0;
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mem_reg_pc <= 32'h0;
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mem_reg_wb_addr <= 5'h0;
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mem_reg_rt_data <= 32'h0;
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mem_reg_mem_wen <= 2'h0;
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mem_reg_rf_wen <= 2'h0;
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mem_reg_wb_sel <= 3'h0;
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mem_reg_alu_out <= 32'h0;
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wb_reg_wb_addr <= 5'h0;
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wb_reg_rf_wen <= 2'h0;
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wb_reg_wb_data <= 32'h0;
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if_reg_pc <= 32'h0;
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end
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else begin
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automatic logic _id_rt_data_T_5;
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automatic logic _id_rt_data_T;
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automatic logic _id_rt_data_T_3;
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automatic logic _id_rt_data_T_6;
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automatic logic _id_rt_data_T_9;
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automatic logic [31:0] id_imm_i_sext;
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automatic logic _csignals_T_1 = id_inst[31:26] == 6'h23;
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automatic logic _csignals_T_3;
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automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
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automatic logic _csignals_T_5 = _GEN_1 == 12'h20;
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automatic logic _csignals_T_7 = id_inst[31:26] == 6'h8;
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automatic logic _csignals_T_9;
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automatic logic _csignals_T_11;
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automatic logic _csignals_T_13;
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automatic logic _csignals_T_15;
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automatic logic _csignals_T_17;
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automatic logic _csignals_T_19;
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automatic logic _csignals_T_21;
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automatic logic _csignals_T_23;
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automatic logic _csignals_T_25;
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automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
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automatic logic _csignals_T_27;
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automatic logic _csignals_T_29;
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automatic logic _csignals_T_31;
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automatic logic _csignals_T_33;
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automatic logic _csignals_T_35;
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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automatic logic [1:0] csignals_1;
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automatic logic [2:0] csignals_2;
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automatic logic _GEN_5;
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automatic logic _GEN_6;
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_id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
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_id_rt_data_T = id_inst[20:16] == 5'h0;
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_id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
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_id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
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_id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
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id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
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_csignals_T_3 = id_inst[31:26] == 6'h2B;
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_csignals_T_9 = _GEN_1 == 12'h22;
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_csignals_T_11 = _GEN_1 == 12'h24;
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_csignals_T_13 = _GEN_1 == 12'h25;
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_csignals_T_15 = _GEN_1 == 12'h26;
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_csignals_T_17 = id_inst[31:26] == 6'hC;
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_csignals_T_19 = id_inst[31:26] == 6'hD;
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_csignals_T_21 = _GEN_1 == 12'h2A;
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_csignals_T_23 = id_inst[31:26] == 6'h4;
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_csignals_T_25 = id_inst[31:26] == 6'h5;
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_csignals_T_27 = _GEN_2 == 17'h0;
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_csignals_T_29 = _GEN_2 == 17'h2;
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_csignals_T_31 = _GEN_2 == 17'h3;
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_csignals_T_33 = id_inst[31:26] == 6'h3;
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_csignals_T_35 = _GEN_1 == 12'h8;
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_GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
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_GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
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csignals_1 =
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_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
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| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
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| _csignals_T_19 | _GEN_4 | ~_csignals_T_33
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? 2'h1
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: 2'h2;
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csignals_2 =
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_csignals_T_1 | _csignals_T_3
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? 3'h2
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: _csignals_T_5
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? 3'h1
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: _csignals_T_7
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? 3'h2
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: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_4
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? 3'h1
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: _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
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_GEN_5 = _csignals_T_23 | _csignals_T_25;
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_GEN_6 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
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if (~stall_flg)
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id_reg_pc <= if_reg_pc;
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if (_id_inst_T)
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id_reg_inst <= 32'h20000000;
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else if (~stall_flg)
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id_reg_inst <= io_imem_inst;
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exe_reg_pc <= id_reg_pc;
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if ((_csignals_T_1
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? 3'h2
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: _csignals_T_3
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? 3'h0
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: _GEN_6
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? 3'h1
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: _GEN_5
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? 3'h0
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: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
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& id_inst[31:26] == 6'h0)
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exe_reg_wb_addr <= id_inst[15:11];
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else if (id_inst[31:26] == 6'h3)
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exe_reg_wb_addr <= 5'h1F;
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else
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exe_reg_wb_addr <= id_inst[20:16];
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if (csignals_1 == 2'h1) begin
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if (id_inst[25:21] == 5'h0)
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exe_reg_op1_data <= 32'h0;
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else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
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if (_exe_alu_out_T)
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exe_reg_op1_data <= _exe_alu_out_T_1;
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else if (_exe_alu_out_T_3)
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exe_reg_op1_data <= _exe_alu_out_T_4;
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else if (_exe_alu_out_T_6)
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exe_reg_op1_data <= _exe_alu_out_T_7;
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else if (_exe_alu_out_T_8)
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exe_reg_op1_data <= _exe_alu_out_T_9;
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else if (_exe_alu_out_T_10)
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exe_reg_op1_data <= _exe_alu_out_T_11;
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else if (_exe_alu_out_T_12)
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exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
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else if (_exe_alu_out_T_16)
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exe_reg_op1_data <= _exe_alu_out_T_18;
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else if (_exe_alu_out_T_19)
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exe_reg_op1_data <= _exe_alu_out_T_22;
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else if (_exe_alu_out_T_24)
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exe_reg_op1_data <= _GEN_0;
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else if (~_exe_alu_out_T_28)
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exe_reg_op1_data <= 32'h0;
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end
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else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
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exe_reg_op1_data <= mem_wb_data;
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else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
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exe_reg_op1_data <= wb_reg_wb_data;
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else
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exe_reg_op1_data <= _regfile_ext_R1_data;
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end
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else if (csignals_1 == 2'h2)
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exe_reg_op1_data <= id_reg_pc;
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else
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exe_reg_op1_data <= 32'h0;
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if (csignals_2 == 3'h1) begin
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if (_id_rt_data_T)
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exe_reg_op2_data <= 32'h0;
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else if (_id_rt_data_T_3) begin
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if (_exe_alu_out_T)
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exe_reg_op2_data <= _exe_alu_out_T_1;
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else if (_exe_alu_out_T_3)
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exe_reg_op2_data <= _exe_alu_out_T_4;
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else if (_exe_alu_out_T_6)
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exe_reg_op2_data <= _exe_alu_out_T_7;
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else if (_exe_alu_out_T_8)
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exe_reg_op2_data <= _exe_alu_out_T_9;
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else if (_exe_alu_out_T_10)
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exe_reg_op2_data <= _exe_alu_out_T_11;
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else if (_exe_alu_out_T_12)
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exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
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else if (_exe_alu_out_T_16)
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exe_reg_op2_data <= _exe_alu_out_T_18;
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else if (_exe_alu_out_T_19)
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exe_reg_op2_data <= _exe_alu_out_T_22;
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else if (_exe_alu_out_T_24)
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exe_reg_op2_data <= _GEN_0;
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else
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exe_reg_op2_data <= _exe_alu_out_T_29;
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end
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else if (_id_rt_data_T_6)
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exe_reg_op2_data <= mem_wb_data;
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else if (_id_rt_data_T_9)
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exe_reg_op2_data <= wb_reg_wb_data;
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else
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exe_reg_op2_data <= _regfile_ext_R0_data;
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end
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else if (csignals_2 == 3'h2)
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exe_reg_op2_data <= id_imm_i_sext;
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else if (csignals_2 == 3'h4)
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exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
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else
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exe_reg_op2_data <= 32'h0;
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exe_reg_rt_data <=
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_id_rt_data_T
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? 32'h0
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: _id_rt_data_T_3
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? exe_alu_out
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: _id_rt_data_T_6
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? mem_wb_data
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: _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
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if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_9)
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exe_reg_exe_fun <= 5'h2;
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else if (_csignals_T_11)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_13)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_15)
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exe_reg_exe_fun <= 5'h5;
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else if (_csignals_T_17)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_19)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_21)
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exe_reg_exe_fun <= 5'h9;
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else if (_csignals_T_23)
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exe_reg_exe_fun <= 5'hB;
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else if (_csignals_T_25)
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exe_reg_exe_fun <= 5'hC;
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else if (_csignals_T_27)
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exe_reg_exe_fun <= 5'h6;
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else if (_csignals_T_29)
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exe_reg_exe_fun <= 5'h7;
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|
else if (_csignals_T_31)
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|
exe_reg_exe_fun <= 5'h8;
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|
else if (_csignals_T_33)
|
|
exe_reg_exe_fun <= 5'h1;
|
|
else if (_csignals_T_35)
|
|
exe_reg_exe_fun <= 5'hD;
|
|
else
|
|
exe_reg_exe_fun <= 5'h0;
|
|
exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
|
|
if (_csignals_T_1) begin
|
|
exe_reg_rf_wen <= 2'h1;
|
|
exe_reg_wb_sel <= 3'h2;
|
|
end
|
|
else if (_csignals_T_3) begin
|
|
exe_reg_rf_wen <= 2'h0;
|
|
exe_reg_wb_sel <= 3'h0;
|
|
end
|
|
else if (_GEN_6) begin
|
|
exe_reg_rf_wen <= 2'h1;
|
|
exe_reg_wb_sel <= 3'h1;
|
|
end
|
|
else if (_GEN_5) begin
|
|
exe_reg_rf_wen <= 2'h0;
|
|
exe_reg_wb_sel <= 3'h0;
|
|
end
|
|
else begin
|
|
exe_reg_rf_wen <=
|
|
{1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
|
|
if (_GEN_3)
|
|
exe_reg_wb_sel <= 3'h1;
|
|
else if (_csignals_T_33)
|
|
exe_reg_wb_sel <= 3'h3;
|
|
else
|
|
exe_reg_wb_sel <= 3'h0;
|
|
end
|
|
exe_reg_imm_i_sext <= id_imm_i_sext;
|
|
mem_reg_pc <= exe_reg_pc;
|
|
mem_reg_wb_addr <= exe_reg_wb_addr;
|
|
mem_reg_rt_data <= exe_reg_rt_data;
|
|
mem_reg_mem_wen <= exe_reg_mem_wen;
|
|
mem_reg_rf_wen <= exe_reg_rf_wen;
|
|
mem_reg_wb_sel <= exe_reg_wb_sel;
|
|
mem_reg_alu_out <= exe_alu_out;
|
|
wb_reg_wb_addr <= mem_reg_wb_addr;
|
|
wb_reg_rf_wen <= mem_reg_rf_wen;
|
|
wb_reg_wb_data <= mem_wb_data;
|
|
if (exe_br_flg)
|
|
if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
|
|
else if (exe_jmp_flg)
|
|
if_reg_pc <= exe_alu_out;
|
|
else if (~stall_flg)
|
|
if_reg_pc <= if_reg_pc + 32'h4;
|
|
end
|
|
end // always @(posedge)
|
|
regfile_32x32 regfile_ext (
|
|
.R0_addr (id_inst[20:16]),
|
|
.R0_en (1'h1),
|
|
.R0_clk (clock),
|
|
.R0_data (_regfile_ext_R0_data),
|
|
.R1_addr (id_inst[25:21]),
|
|
.R1_en (1'h1),
|
|
.R1_clk (clock),
|
|
.R1_data (_regfile_ext_R1_data),
|
|
.W0_addr (wb_reg_wb_addr),
|
|
.W0_en (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
|
|
.W0_clk (clock),
|
|
.io_anodes (io_anodes),
|
|
.io_segments (io_segments),
|
|
.W0_data (wb_reg_wb_data)
|
|
);
|
|
assign io_imem_addr = if_reg_pc;
|
|
assign io_dmem_addr = mem_reg_alu_out;
|
|
assign io_dmem_wen = mem_reg_mem_wen[0];
|
|
assign io_dmem_wdata = mem_reg_rt_data;
|
|
assign io_exit = id_reg_inst == 32'h114514;
|
|
endmodule
|