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CGH0S7 7ae5ee8c39 SystemVerilog Module Complete
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micore.xdc
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README.md
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Regfile.sv
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testbench.sv
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Top.sv
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README.md

micore

五级流水线MIPS处理器设计

Description
五级流水线MIPS处理器设计
Readme 2.8 MiB
Languages
SystemVerilog 60.7%
Scala 37%
Tcl 2.3%