[backend-IRC]修复了极其隐蔽的寄存器分配问题

This commit is contained in:
Lixuanwang
2025-08-01 17:29:18 +08:00
parent 8fe9867f33
commit 373726b02f

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@ -157,7 +157,7 @@ void RISCv64RegAlloc::precolorByCallingConvention() {
// 修改部分将物理寄存器ID转换为其字符串名称
for (unsigned v : precolored) std::cerr << regIdToString(v) << " ";
std::cerr << "}\nColored nodes: { ";
for (unsigned v : coloredNodes) std::cerr << "%vreg" << v << " ";
for (unsigned v : coloredNodes) std::cerr << "<%vreg" << v << ", " << regToString(color_map.at(v)) << "> ";
std::cerr << "}\n";
}
}
@ -283,7 +283,7 @@ void RISCv64RegAlloc::build() {
if (precolored.count(v)) {
std::cerr << "Skipping " << regIdToString(v) << " because it is a physical register.\n";
} else {
std::cerr << "Skipping " << regIdToString(v) << " because it is a pre-colored virtual register.\n";
std::cerr << "Skipping " << regIdToString(v) << " because it is a pre-colored virtual register with " << regToString(color_map.at(v)) << "\n";
}
}
}
@ -294,7 +294,7 @@ void RISCv64RegAlloc::build() {
if (precolored.count(v)) {
std::cerr << "Skipping " << regIdToString(v) << " because it is a physical register.\n";
} else {
std::cerr << "Skipping " << regIdToString(v) << " because it is a pre-colored virtual register.\n";
std::cerr << "Skipping " << regIdToString(v) << " because it is a pre-colored virtual register with " << regToString(color_map.at(v)) << ".\n";
}
}
}
@ -611,7 +611,6 @@ void RISCv64RegAlloc::selectSpill() {
void RISCv64RegAlloc::assignColors() {
if (DEEPDEBUG) std::cerr << "[AssignColors] Starting...\n";
// 步骤 1: 为 selectStack 中的节点分配颜色 (此部分逻辑不变)
while (!selectStack.empty()) {
unsigned n = selectStack.back();
@ -983,7 +982,7 @@ void RISCv64RegAlloc::addEdge(unsigned u, unsigned v) {
if (u == v) return;
// 检查两个节点是否都是虚拟寄存器
if (!precolored.count(u) && !precolored.count(v)) {
if (!precolored.count(u) && !precolored.count(v) && !coloredNodes.count(u) && !coloredNodes.count(v)) {
// 只有当两个都是虚拟寄存器时,才为它们双方添加边和更新度数
// 使用 operator[] 是安全的如果键不存在它会默认构造一个空的set
if (adjList[u].find(v) == adjList[u].end()) {
@ -994,7 +993,7 @@ void RISCv64RegAlloc::addEdge(unsigned u, unsigned v) {
}
}
// 检查是否为 "虚拟-物理" 对
else if (!precolored.count(u) && precolored.count(v)) {
else if (!precolored.count(u) && precolored.count(v) && !coloredNodes.count(u)) {
// u是虚拟寄存器v是物理寄存器只更新u的邻接表和度数
if (adjList[u].find(v) == adjList[u].end()) {
adjList[u].insert(v);
@ -1002,7 +1001,7 @@ void RISCv64RegAlloc::addEdge(unsigned u, unsigned v) {
}
}
// 检查是否为 "物理-虚拟" 对
else if (precolored.count(u) && !precolored.count(v)) {
else if (precolored.count(u) && !precolored.count(v) && !coloredNodes.count(v)) {
// u是物理寄存器v是虚拟寄存器只更新v的邻接表和度数
if (adjList[v].find(u) == adjList[v].end()) {
adjList[v].insert(u);
@ -1122,8 +1121,14 @@ void RISCv64RegAlloc::decrementDegree(unsigned m) {
enableMoves(nodes_to_enable);
spillWorklist.erase(m);
if (moveRelated(m)) {
if (DEEPDEBUG) {
std::cerr << "[decrementDegree] Node " << regIdToString(m) << " has degree " << d << ", now decremented to " << degree.at(m) << ". Added to freezeWorklist.\n";
}
freezeWorklist.insert(m);
} else {
if (DEEPDEBUG) {
std::cerr << "[decrementDegree] Node " << regIdToString(m) << " has degree " << d << ", now decremented to " << degree.at(m) << ". Added to simplifyWorklist.\n";
}
simplifyWorklist.insert(m);
}
}
@ -1160,6 +1165,9 @@ void RISCv64RegAlloc::addWorklist(unsigned u) {
if (!moveRelated(u) && degree.at(u) < K) {
freezeWorklist.erase(u);
simplifyWorklist.insert(u);
if (DEEPDEBUG) {
std::cerr << "[addWorklist] Node " << regIdToString(u) << " added to simplifyWorklist (degree: " << degree.at(u) << ", K: " << K << ").\n";
}
}
}
@ -1317,6 +1325,9 @@ void RISCv64RegAlloc::freezeMoves(unsigned u) {
if (!precolored.count(v_alias) && nodeMoves(v_alias).empty() && degree.at(v_alias) < (isFPVReg(v_alias) ? K_fp : K_int)) {
freezeWorklist.erase(v_alias);
simplifyWorklist.insert(v_alias);
if (DEEPDEBUG) {
std::cerr << "[freezeMoves] Node " << regIdToString(v_alias) << " moved to simplifyWorklist (degree: " << degree.at(v_alias) << ").\n";
}
}
}
}