Bump rocketchip to latest, chisel to 3.5.2

Remove fork of BusTopologies from rocket-chip

Update generators/chipyard/src/main/scala/config/AbstractConfig.scala

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

build.sbt

@@ -60,7 +60,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.5.1"
+val chiselVersion = "3.5.2"
 
 lazy val chiselSettings = Seq(
   libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,

generators/chipyard/src/main/scala/CustomBusTopologies.scala

@@ -1,82 +0,0 @@
-
-package chipyard
-
-import freechips.rocketchip.config.{Field, Config, Parameters}
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.{Location, Symmetric}
-import freechips.rocketchip.subsystem._
-
-// I'm putting this code here temporarily as I think it should be a candidate
-// for upstreaming based on input from Henry Cook, but don't wnat to deal with
-// an RC branch just yet.
-
-// For subsystem/BusTopology.scala
-
-// Biancolin: This, modified from Henry's email
-/** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */
-case class CoherentMulticlockBusTopologyParams(
-  sbus: SystemBusParams, // TODO remove this after better width propagation
-  mbus: MemoryBusParams,
-  l2: BankedL2Params,
-  sbusToMbusXType: ClockCrossingType = NoCrossing
-) extends TLBusWrapperTopology(
-  instantiations = (if (l2.nBanks == 0) Nil else List(
-    (MBUS, mbus),
-    (L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, L2.name)(l2.coherenceManager)))),
-  connections = if (l2.nBanks == 0) Nil else List(
-    (SBUS, L2,   TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
-    (L2,  MBUS,  TLBusWrapperConnection.crossTo(
-      xType = sbusToMbusXType,
-      driveClockFromMaster = None,
-      nodeBinding = BIND_QUERY))
-  )
-)
-
-// This differs from upstream only in that it does not use the legacy crossTo
-// and crossFrom functions, and it ensures driveClockFromMaster = None
-case class HierarchicalMulticlockBusTopologyParams(
-  pbus: PeripheryBusParams,
-  fbus: FrontBusParams,
-  cbus: PeripheryBusParams,
-  xTypes: SubsystemCrossingParams
-) extends TLBusWrapperTopology(
-  instantiations = List(
-    (PBUS, pbus),
-    (FBUS, fbus),
-    (CBUS, cbus)),
-  connections = List(
-    (SBUS, CBUS, TLBusWrapperConnection.  crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)),
-    (CBUS, PBUS, TLBusWrapperConnection.  crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)),
-    (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None)))
-)
-
-// For subsystem/Configs.scala
-
-class WithMulticlockCoherentBusTopology extends Config((site, here, up) => {
-  case TLNetworkTopologyLocated(InSubsystem) => List(
-    JustOneBusTopologyParams(sbus = site(SystemBusKey)),
-    HierarchicalMulticlockBusTopologyParams(
-      pbus = site(PeripheryBusKey),
-      fbus = site(FrontBusKey),
-      cbus = site(ControlBusKey),
-      xTypes = SubsystemCrossingParams(
-        sbusToCbusXType = site(SbusToCbusXTypeKey),
-        cbusToPbusXType = site(CbusToPbusXTypeKey),
-        fbusToSbusXType = site(FbusToSbusXTypeKey))),
-    CoherentMulticlockBusTopologyParams(
-      sbus = site(SystemBusKey),
-      mbus = site(MemoryBusKey),
-      l2 = site(BankedL2Key),
-      sbusToMbusXType = site(SbusToMbusXTypeKey)))
-})
-
-class WithMulticlockIncoherentBusTopology extends Config((site, here, up) => {
-  case TLNetworkTopologyLocated(InSubsystem) => List(
-    JustOneBusTopologyParams(sbus = site(SystemBusKey)),
-    HierarchicalMulticlockBusTopologyParams(
-      pbus = site(PeripheryBusKey),
-      fbus = site(FrontBusKey),
-      cbus = site(ControlBusKey),
-      xTypes = SubsystemCrossingParams()))
-})

generators/chipyard/src/main/scala/Subsystem.scala

@@ -13,8 +13,6 @@ import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._

generators/chipyard/src/main/scala/System.scala

@@ -60,7 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
   private val device = new MemoryDevice
   private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
 
-  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
+  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
     Seq.tabulate(nMemoryChannels) { channel =>
       val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
       val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -41,20 +41,21 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithCustomBootPin ++
   new chipyard.iobinders.WithDividerOnlyClockGenerator ++
 
-  new testchipip.WithSerialTLWidth(32) ++                        // fatten the serialTL interface to improve testing performance
+  new testchipip.WithSerialTLWidth(32) ++                           // fatten the serialTL interface to improve testing performance
-  new testchipip.WithDefaultSerialTL ++                          // use serialized tilelink port to external serialadapter/harnessRAM
+  new testchipip.WithDefaultSerialTL ++                             // use serialized tilelink port to external serialadapter/harnessRAM
-  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithBootROM ++                                // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
+  new chipyard.config.WithUART ++                                   // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+  new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
-  new chipyard.config.WithNoSubsystemDrivenClocks ++             // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
+  new chipyard.config.WithNoSubsystemDrivenClocks ++                // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
-  new chipyard.config.WithInheritBusFrequencyAssignments ++      // Unspecified clocks within a bus will receive the bus frequency if set
+  new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
-  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++      // Unspecified frequencies with match the pbus frequency (which is always set)
+  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++         // Unspecified frequencies with match the pbus frequency (which is always set)
-  new chipyard.config.WithMemoryBusFrequency(100.0) ++           // Default 100 MHz mbus
+  new chipyard.config.WithMemoryBusFrequency(100.0) ++              // Default 100 MHz mbus
-  new chipyard.config.WithPeripheryBusFrequency(100.0) ++        // Default 100 MHz pbus
+  new chipyard.config.WithPeripheryBusFrequency(100.0) ++           // Default 100 MHz pbus
-  new freechips.rocketchip.subsystem.WithJtagDTM ++              // set the debug module to expose a JTAG port
+  new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++              // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++             // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++          // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++    // no external interrupts
-  new chipyard.WithMulticlockCoherentBusTopology ++              // hierarchical buses including mbus+l2
+  new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
+  new freechips.rocketchip.system.BaseConfig)                       // "base" rocketchip system

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -15,7 +15,7 @@ class TinyRocketConfig extends Config(
   new chipyard.config.WithTLSerialLocation(
     freechips.rocketchip.subsystem.FBUS,
     freechips.rocketchip.subsystem.PBUS) ++                       // attach TL serial adapter to f/p busses
-  new chipyard.WithMulticlockIncoherentBusTopology ++             // use incoherent bus topology
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
   new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
   new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
   new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -7,7 +7,6 @@ import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode}
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.subsystem.{RocketCrossingParams}
 import freechips.rocketchip.tilelink._

generators/firechip/src/main/scala/FireSim.scala

@@ -262,9 +262,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna
     // instantiation of the dut, otherwise the initial instance will be
     // reused across each node
     import freechips.rocketchip.subsystem.AsyncClockGroupsKey
-    val lazyModule = LazyModule(p(BuildTop)(p.alterPartial({
+    val lazyModule = LazyModule(p(BuildTop)(p))
-      case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
-    })))
     val module = Module(lazyModule.module)
 
     lazyModule match { case d: HasIOBinders =>