Consolidate peripheral device testing configs into a single ManyPeripheralsConfig

.github/scripts/defaults.sh

@@ -31,7 +31,7 @@ JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX)
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif chipyard-nocores"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals"
 grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -42,7 +42,6 @@ grouping["group-fpga"]="arty vcu118 vc707"
 declare -A mapping
 mapping["chipyard-rocket"]=""
 mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
-mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig"
 mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
 mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
 mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
@@ -51,14 +50,12 @@ mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketCon
 mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
 mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
 mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
-mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
 mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
 mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
-mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
-mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
+mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"

.github/scripts/run-tests.sh

@@ -35,9 +35,6 @@ case $1 in
     chipyard-dmirocket)
         run_bmark ${mapping[$1]}
         ;;
-    chipyard-lbwif)
-        run_bmark ${mapping[$1]}
-        ;;
     chipyard-boom)
         run_bmark ${mapping[$1]}
         ;;
@@ -77,7 +74,10 @@ case $1 in
         make -C $LOCAL_CHIPYARD_DIR/tests
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv
         ;;
-    chipyard-spiflashread)
+    chipyard-manyperipherals)
+	# bmark tests, then SPI Flash read tests
+        run_bmark ${mapping[$1]}
+
         make -C $LOCAL_CHIPYARD_DIR/tests
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary-fast
         ;;

.github/workflows/chipyard-run-tests.yml

@@ -620,31 +620,8 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-spiflashwrite"
 
-  chipyard-spiflashread-run-tests:
-    name: chipyard-spiflashread-run-tests
-    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
-    steps:
-      - name: Delete old checkout
-        run: |
-          ls -alh .
-          rm -rf ${{ github.workspace }}/* || true
-          rm -rf ${{ github.workspace }}/.* || true
-          ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-peripherals"
-          project-key: "chipyard-spiflashread"
-
-  chipyard-lbwif-run-tests:
-    name: chipyard-lbwif-run-tests
+  chipyard-manyperipherals-run-tests:
+    name: chipyard-manyperipherals-run-tests
     needs: prepare-chipyard-peripherals
     runs-on: self-hosted
     steps:
@@ -664,7 +641,7 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-peripherals"
-          project-key: "chipyard-lbwif"
+          project-key: "chipyard-manyperipherals"
 
   chipyard-sha3-run-tests:
     name: chipyard-sha3-run-tests
@@ -1009,9 +986,8 @@ jobs:
             chipyard-sodor-run-tests,
             chipyard-dmirocket-run-tests,
             chipyard-fftgenerator-run-tests,
-            chipyard-spiflashread-run-tests,
             chipyard-spiflashwrite-run-tests,
-            chipyard-lbwif-run-tests,
+            chipyard-manyperipherals-run-tests,
             chipyard-sha3-run-tests,
             chipyard-streaming-fir-run-tests,
             chipyard-streaming-passthrough-run-tests,

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -63,3 +63,15 @@ class dmiRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DmiRocket
+
+class ManyPeripheralsRocketConfig extends Config(
+  new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
+  new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+  new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
+  new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
+  new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
+  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
+  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)