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Increase debug module data capacity

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This commit is contained in:
Jerry Zhao
2023-04-17 11:56:12 -07:00
parent 2ec45b4f63
commit 07e19e5bb8
2 changed files with 5 additions and 0 deletions
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1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -48,6 +48,7 @@ class AbstractConfig extends Config(
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs

4
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
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@@ -87,3 +87,7 @@ class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
class WithNoPLIC extends Config((site, here, up) => { class WithNoPLIC extends Config((site, here, up) => {
case PLICKey => None case PLICKey => None
}) })
class WithDebugModuleAbstractDataWords(words: Int = 16) extends Config((site, here, up) => {
case DebugModuleKey => up(DebugModuleKey).map(_.copy(nAbstractDataWords=words))
})