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Merge pull request #1487 from jerryhethatday/bug-fix-jerryho

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(VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus
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Jerry Zhao
2023-05-27 10:38:16 -07:00
committed by GitHub
parent c1ad70c10f 9844deb172
commit 0b07958e6c
1 changed files with 1 additions and 1 deletions
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2
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -84,7 +84,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
name = "chip_ddr",
sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
)))))
ddrNode := ddrClient
ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
// module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this)