Switch FIR from UInt -> FixedPoint
This commit is contained in:
@@ -22,6 +22,8 @@ class DigitalTop(implicit p: Parameters) extends System
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with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
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with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
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with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
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with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget
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with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget
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{
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override lazy val module = new DigitalTopModule(this)
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}
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@@ -3,7 +3,7 @@
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package chipyard.example
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import chisel3._
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import chisel3.{Bundle, Module}
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import chisel3.experimental.FixedPoint
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import chisel3.util._
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import dspblocks._
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import dsptools.numbers._
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@@ -80,9 +80,9 @@ class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module
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// Connect adjacent cells
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// Note that .tail() returns a collection that consists of all
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// elements in the inital collection minus the first one.
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// This means that we zip together directCells[0, n] and
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// This means that we zip together directCells[0, n] and
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// directCells[1, n]. However, since zip ignores unmatched elements,
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// the resulting zip is (directCells[0], directCells[1]) ...
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// the resulting zip is (directCells[0], directCells[1]) ...
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// (directCells[n-1], directCells[n])
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for ((current, next) <- directCells.zip(directCells.tail)) {
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next.in.bits := current.out.bits
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@@ -108,22 +108,22 @@ class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module
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//
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// DOC include start: GenericFIRDirectCell chisel
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class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
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val io = IO(GenericFIRCellIO(genIn, genOut))
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val io = IO(GenericFIRCellIO(genIn, genOut))
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// Registers to delay the input and the valid to propagate with calculations
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val hasNewData = RegInit(0.U)
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val inputReg = Reg(genIn.cloneType)
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// Passthrough ready
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io.in.ready := io.out.ready
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// When a new transaction is ready on the input, we will have new data to output
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// next cycle. Take this data in
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when (io.in.fire()) {
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hasNewData := 1.U
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inputReg := io.in.bits.data
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inputReg := io.in.bits.data
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}
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// We should output data when our cell has new data to output and is ready to
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// recieve new data. This insures that every cell in the chain passes its data
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// on at the same time
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@@ -133,7 +133,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
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// Compute carry
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// This uses the ring implementation for + and *, i.e.
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// (a * b) maps to (Ring[T].prod(a, b)) for whicever T you use
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io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry
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io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry
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}
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// DOC include end: GenericFIRDirectCell chisel
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@@ -204,8 +204,12 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para
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trait CanHavePeripheryUIntTestFIR extends BaseSubsystem {
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val fir = p(GenericFIRKey) match {
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case Some(params) => {
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val fir = LazyModule(new TLGenericFIRChain(UInt(8.W), UInt(12.W), Seq(1.U, 2.U, 3.U), params))
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val fir = LazyModule(new TLGenericFIRChain(
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genIn = FixedPoint(8.W, 3.BP),
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genOut = FixedPoint(8.W, 3.BP),
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coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
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params = params))
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pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get }
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pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get }
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}
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28
tests/fir.c
28
tests/fir.c
@@ -3,6 +3,9 @@
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#define PASSTHROUGH_READ 0x2100
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#define PASSTHROUGH_READ_COUNT 0x2108
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#define BP 3
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#define BP_SCALE ((double)(1 << BP))
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#include "mmio.h"
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#include <stdio.h>
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@@ -10,14 +13,23 @@
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#include <string.h>
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#include <stdint.h>
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uint64_t roundi(double x)
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{
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if (x < 0.0) {
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return (uint64_t)(x - 0.5);
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} else {
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return (uint64_t)(x + 0.5);
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}
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}
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int main(void)
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{
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printf("Starting writing\n");
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uint32_t num_tests = 15;
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uint32_t test_vector[15] = {1, 2, 3, 4, 5, 4, 3, 2, 1, 5, 4, 3, 2, 1, 2};
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double test_vector[15] = {1.0, 2.0, 3.0, 4.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.5, 0.25, 0.125, 0.125};
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uint32_t num_tests = sizeof(test_vector) / sizeof(double);
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printf("Starting writing %d inputs\n", num_tests);
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for (int i = 0; i < num_tests; i++) {
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reg_write64(PASSTHROUGH_WRITE, test_vector[i]);
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reg_write64(PASSTHROUGH_WRITE, roundi(test_vector[i] * BP_SCALE));
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}
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printf("Done writing\n");
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@@ -29,12 +41,14 @@ int main(void)
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if (rcnt != 0) {
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for (int i = 0; i < num_tests - 3; i++) {
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uint32_t res = reg_read32(PASSTHROUGH_READ);
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uint32_t expected = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2];
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// double res = ((double)reg_read32(PASSTHROUGH_READ)) / BP_SCALE;
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double expected_double = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2];
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uint32_t expected = ((uint32_t)(expected_double * BP_SCALE + 0.5)) & 0xFF;
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if (res == expected) {
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printf("\n\nPass: Got %d Expected %d\n\n", res, expected);
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printf("\n\nPass: Got %u Expected %u\n\n", res, expected);
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} else {
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failed = 1;
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printf("\n\nFail: Got %d Expected %d\n\n", res, expected);
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printf("\n\nFail: Got %u Expected %u\n\n", res, expected);
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}
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}
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} else {
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