fix test harness builds

README.md

@@ -2,7 +2,7 @@
 
 **This branch is under development**
 **It currently has many submodules**
-**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodule to clone**
+**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodules to clone**
 
 This is a starter template for your custom RISC-V project. It will allow you
 to leverage the Chisel HDL and RocketChip SoC generator to produce a

common.mk

@@ -53,7 +53,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI
 	cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
 
 $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
-	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(FIRRTL_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
 	grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs

src/main/scala/example/TestHarness.scala

@@ -18,6 +18,9 @@ class RocketTestHarness(implicit val p: Parameters) extends Module {
     val success = Output(Bool())
   })
 
+  // force Chisel to rename module
+  override def desiredName = "TestHarness"
+
   val dut = p(BuildRocketTop)(clock, reset.toBool, p)
   dut.debug := DontCare
   dut.connectSimAXIMem()
@@ -51,6 +54,9 @@ class BoomTestHarness(implicit val p: Parameters) extends Module {
     val success = Output(Bool())
   })
 
+  // force Chisel to rename module
+  override def desiredName = "TestHarness"
+
   val dut = p(BuildBoomTop)(clock, reset.toBool, p)
   dut.debug := DontCare
   dut.connectSimAXIMem()

variables.mk

@@ -6,7 +6,8 @@
 # default variables to invoke the generator for a example Rocket system
 # descriptions:
 #   PROJECT = the scala package to find the MODEL/Generator in
-#   MODEL = the top level module of the project (normally the harness)
+#   MODEL = the top level module of the project in Chisel (normally the harness)
+#   FIRRTL_MODEL = the top level module of the project in Firrtl (normally the harness)
 #   CONFIG = the configuration class to give the parameters for the project
 #   CFG_PROJECT = the scala package to find the CONFIG class
 #   SBT_PROJECT = the SBT project that you should find the Generator class in
@@ -16,13 +17,14 @@
 # project specific:
 # 	SUB_PROJECT = use the specific subproject default variables
 #########################################################################################
-PROJECT     ?= example
-MODEL       ?= RocketTestHarness
-CONFIG      ?= DefaultRocketConfig
-CFG_PROJECT ?= $(PROJECT)
-SBT_PROJECT ?= $(PROJECT)
-TB          ?= TestDriver
-TOP         ?= RocketTop
+PROJECT      ?= example
+MODEL        ?= RocketTestHarness
+FIRRTL_MODEL ?= TestHarness
+CONFIG       ?= DefaultRocketConfig
+CFG_PROJECT  ?= $(PROJECT)
+SBT_PROJECT  ?= $(PROJECT)
+TB           ?= TestDriver
+TOP          ?= RocketTop
 
 # make it so that you only change 1 param to change most or all of them!
 SUB_PROJECT ?= example
@@ -36,7 +38,6 @@ ifeq ($(SUB_PROJECT),boom)
 	# for BOOM developers (only need to provide a CONFIG)
 	PROJECT=boom.system
 	MODEL=TestHarness
-	#CONFIG: User specified
 	CFG_PROJECT=boom.system
 	SBT_PROJECT=boom
 	TOP=ExampleBoomSystem