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Update nexysvideo to Port api

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This commit is contained in:
Jerry Zhao
2023-10-09 11:49:38 -07:00
parent 8ecd7bfa89
commit 0ebab140ff
1 changed files with 12 additions and 16 deletions
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28
fpga/src/main/scala/nexysvideo/HarnessBinders.scala
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@@ -14,30 +14,26 @@ import chipyard._
import chipyard.harness._ import chipyard.harness._
import testchipip._ import testchipip._
import chipyard.iobinders._
class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
(system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => { case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
require(ports.size <= 1)
val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness] val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
ports.map({ port => nexysvideoth.io_uart_bb.bundle <> port.io.uart
nexysvideoth.io_uart_bb.bundle <> port.uart nexysvideoth.other_leds(1) := port.io.dropped
nexysvideoth.other_leds(1) := port.dropped nexysvideoth.other_leds(2) := port.io.tsi2tl_state(0)
nexysvideoth.other_leds(2) := port.tsi2tl_state(0) nexysvideoth.other_leds(3) := port.io.tsi2tl_state(1)
nexysvideoth.other_leds(3) := port.tsi2tl_state(1) nexysvideoth.other_leds(4) := port.io.tsi2tl_state(2)
nexysvideoth.other_leds(4) := port.tsi2tl_state(2) nexysvideoth.other_leds(5) := port.io.tsi2tl_state(3)
nexysvideoth.other_leds(5) := port.tsi2tl_state(3)
})
} }
}) })
class WithNexysVideoDDRTL extends OverrideHarnessBinder({ class WithNexysVideoDDRTL extends HarnessBinder({
(system: CanHaveMasterTLMemPort, th: HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => { case (th: HasHarnessInstantiators, port: TLMemPort) => {
require(ports.size == 1)
val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness] val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
val bundles = nexysTh.ddrClient.get.out.map(_._1) val bundles = nexysTh.ddrClient.get.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
ddrClientBundle <> ports.head ddrClientBundle <> port.io
} }
}) })