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Bump rocket-chip

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This commit is contained in:
Jerry Zhao
2023-10-20 15:07:18 -07:00
parent 1d9dba517b
commit 127a759629
4 changed files with 8 additions and 5 deletions
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2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -53,7 +53,7 @@ class AbstractConfig extends Config(
// By default, punch out IOs to the Harness
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus

3
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
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@@ -12,10 +12,11 @@ class AbstractTraceGenConfig extends Config(
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
new chipyard.config.WithTracegenSystem ++
new chipyard.config.WithNoSubsystemClockIO ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 8881ccd1ca...0e88fc066e

6
generators/tracegen/src/main/scala/System.scala
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@@ -23,11 +23,13 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
lazy val fakeClockDomain = sbus.generateSynchronousDomain
lazy val clintOpt = None
lazy val debugOpt = None
lazy val plicOpt = None
lazy val clintDomainOpt = None
lazy val plicDomainOpt = None
lazy val clintDomainOpt = Some(fakeClockDomain)
lazy val plicDomainOpt = Some(fakeClockDomain)
override lazy val module = new TraceGenSystemModuleImp(this)
}