Update names | Fix find-config-frags

This commit is contained in:
abejgonzalez
2023-05-24 09:22:49 -07:00
parent 34263fe1a6
commit 1363d82813
2 changed files with 10 additions and 10 deletions

View File

@@ -102,12 +102,12 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
#########################################################################################
# compile scala jars
#########################################################################################
$(GEN_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
$(CHIPYARD_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,$(SBT_PROJECT),$(GEN_CLASSPATH))
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
# order only dependency between sbt runs needed to avoid concurrent sbt runs
$(BTL_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(GEN_CLASSPATH_TARGETS)
$(BTL_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(BTL_CLASSPATH))
@@ -115,9 +115,9 @@ $(BTL_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(GEN_CLA
# verilog generation pipeline
#########################################################################################
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(GEN_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir)
(set -o pipefail && $(call run_jar_scala_main,$(GEN_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
(set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
--target-dir $(build_dir) \
--name $(long_name) \
--top-module $(MODEL_PACKAGE).$(MODEL) \
@@ -392,7 +392,7 @@ endef
.PHONY: find-config-fragments
find-config-fragments:
$(call run_jar_scala_main,chipyard,chipyard.ConfigFinder,)
$(call run_scala_main,chipyard,chipyard.ConfigFinder,)
.PHONY: help
help:

View File

@@ -146,11 +146,11 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
endif
# classpaths
GEN_CLASSPATH ?= $(gen_dir)/chipyard-generator.jar
BTL_CLASSPATH ?= $(gen_dir)/barstools.jar
CHIPYARD_CLASSPATH ?= $(gen_dir)/chipyard.jar
TAPEOUT_CLASSPATH ?= $(gen_dir)/tapeout.jar
# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
GEN_CLASSPATH_TARGETS ?= $(subst :, ,$(GEN_CLASSPATH))
BTL_CLASSPATH_TARGETS ?= $(subst :, ,$(BTL_CLASSPATH))
CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))
# chisel generated outputs
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir