Merge pull request #512 from ucb-bar/hammer-sim-integration

Hammer sim integration

sims/vcs/Makefile

@@ -25,7 +25,7 @@ sim_prefix = simv
 sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
 sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
 
-WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
+include $(base_dir)/vcs.mk
 
 .PHONY: default debug
 default: $(sim)
@@ -41,42 +41,7 @@ include $(base_dir)/common.mk
 #########################################################################################
 VCS = vcs -full64
 
-VCS_CC_OPTS = \
+VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES)
-	-CC "-I$(VCS_HOME)/include" \
-	-CC "-I$(RISCV)/include" \
-	-CC "-I$(dramsim_dir)" \
-	-CC "-std=c++11" \
-	$(dramsim_lib) \
-	$(RISCV)/lib/libfesvr.a \
-	-CC "$(EXTRA_SIM_CC_FLAGS)"
-
-VCS_NONCC_OPTS = \
-	+lint=all,noVCDE,noONGS,noUI \
-	-timescale=1ns/1ps \
-	-quiet \
-	-q \
-	+rad \
-	+vcs+lic+wait \
-	+vc+list \
-	-error=noZMMCM \
-	-error=PCWM-L \
-	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
-	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-	+incdir+$(build_dir) \
-	-f $(sim_common_files) \
-	$(sim_vsrcs)
-
-VCS_DEFINES = \
-	+define+VCS \
-	+define+CLOCK_PERIOD=1.0 \
-	+define+PRINTF_COND=$(TB).printf_cond \
-	+define+STOP_COND=!$(TB).reset \
-	+define+RANDOMIZE_MEM_INIT \
-	+define+RANDOMIZE_REG_INIT \
-	+define+RANDOMIZE_GARBAGE_ASSIGN \
-	+define+RANDOMIZE_INVALID_ASSIGN
-
-VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) $(EXTRA_SIM_SOURCES)
 
 #########################################################################################
 # vcs simulator rules

vcs.mk

@@ -0,0 +1,42 @@
+WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
+
+CLOCK_PERIOD ?= 1.0
+RESET_DELAY ?= 777.7
+
+VCS_CC_OPTS = \
+	-CC "-I$(RISCV)/include" \
+	-CC "-I$(dramsim_dir)" \
+	-CC "-std=c++11" \
+	-CC "$(EXTRA_SIM_CC_FLAGS)"
+
+VCS_NONCC_OPTS = \
+	$(dramsim_lib) \
+	$(RISCV)/lib/libfesvr.a \
+	+lint=all,noVCDE,noONGS,noUI \
+	-error=PCWM-L \
+	-error=noZMMCM \
+	-timescale=1ns/10ps \
+	-quiet \
+	-q \
+	+rad \
+	+v2k \
+	+vcs+lic+wait \
+	+vc+list \
+	-f $(sim_common_files) \
+	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
+	-debug_pp \
+	+incdir+$(build_dir) \
+	$(sim_vsrcs) \
+	+libext+.v
+
+VCS_DEFINE_OPTS = \
+	+define+VCS \
+	+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
+	+define+RESET_DELAY=$(RESET_DELAY) \
+	+define+PRINTF_COND=$(TB).printf_cond \
+	+define+STOP_COND=!$(TB).reset \
+	+define+RANDOMIZE_MEM_INIT \
+	+define+RANDOMIZE_REG_INIT \
+	+define+RANDOMIZE_GARBAGE_ASSIGN \
+	+define+RANDOMIZE_INVALID_ASSIGN

vlsi/Makefile

@@ -67,8 +67,8 @@ include $(base_dir)/common.mk
 #########################################################################################
 # srams
 #########################################################################################
-SRAM_GENERATOR_CONF = $(build_dir)/sram_generator-input.yml
+SRAM_GENERATOR_CONF = $(OBJ_DIR)/sram_generator-input.yml
-SRAM_CONF=$(build_dir)/sram_generator-output.json
+SRAM_CONF=$(OBJ_DIR)/sram_generator-output.json
 
 ## SRAM Generator
 .PHONY: sram_generator srams
@@ -87,6 +87,88 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
 	cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
 	cd $(vlsi_dir) && cp output.json $@
 
+#########################################################################################
+# simulation input configuration
+#########################################################################################
+include $(base_dir)/vcs.mk
+SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
+SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
+SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
+
+include $(vlsi_dir)/sim.mk
+$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
+	mkdir -p $(dir $@)
+	echo "sim.inputs:" > $@
+	echo "  top_module: $(VLSI_TOP)" >> $@
+	echo "  input_files:" >> $@
+	for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  input_files_meta: 'append'" >> $@
+	echo "  timescale: '1ns/10ps'" >> $@
+	echo "  options:" >> $@
+	for x in $(VCS_NONCC_OPTS); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  options_meta: 'append'" >> $@
+	echo "  defines:" >> $@
+	for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  defines_meta: 'append'" >> $@
+	echo "  compiler_opts:" >> $@
+	for x in $(filter-out -CC,$(VCS_CC_OPTS)); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  compiler_opts_meta: 'append'" >> $@
+	echo "  execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
+	echo "  execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
+	echo "  execution_flags:" >> $@
+	for x in $(SIM_FLAGS); do \
+	  echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  execution_flags_meta: 'append'" >> $@
+	echo "  benchmarks: ['$(BINARY)']" >> $@
+	echo "  tb_dut: 'testHarness.top'" >> $@
+
+$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
+	mkdir -p $(dir $@)
+	echo "sim.inputs:" > $@
+	echo "  defines: ['DEBUG']" >> $@
+	echo "  defines_meta: 'append'" >> $@
+	echo "  execution_flags:" >> $@
+	for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
+	  echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  execution_flags_meta: 'append'" >> $@
+	echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
+
+$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
+	mkdir -p $(dir $@)
+	echo "sim.inputs:" > $@
+	echo "  defines: ['NTC']" >> $@
+	echo "  defines_meta: 'append'" >> $@
+	echo "  timing_annotated: 'true'" >> $@
+
+POWER_CONF = $(OBJ_DIR)/power-inputs.yml
+include $(vlsi_dir)/power.mk
+LOWER_VLSI_TOP = $(shell echo $(VLSI_TOP) | tr A-Z a-z)
+$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
+	mkdir -p $(dir $@)
+	echo "power.inputs:" > $@
+	echo "  tb_dut: 'testHarness/$(LOWER_VLSI_TOP)'" >> $@
+	echo "  database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
+	echo "  saifs: [" >> $@
+	echo "    '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@
+	echo "  ]" >> $@
+	echo "  waveforms: [" >> $@
+	#echo "    '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@
+	echo "  ]" >> $@
+	echo "  start_times: ['0ns']" >> $@
+	echo "  end_times: [" >> $@
+	echo "    '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
+	echo "  ]" >> $@
+
 #########################################################################################
 # synthesis input configuration
 #########################################################################################
@@ -98,10 +180,16 @@ endif
 
 $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
 	mkdir -p $(dir $@)
-	echo "synthesis.inputs:" > $@
+	echo "sim.inputs:" > $@
+	echo "  input_files:" >> $@
+	for x in $(VLSI_RTL); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  input_files_meta: 'append'" >> $@
+	echo "synthesis.inputs:" >> $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  input_files:" >> $@
-	for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \
+	for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 
@@ -124,4 +212,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
 #########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir)
+	rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)

vlsi/power.mk

@@ -0,0 +1,6 @@
+.PHONY: $(POWER_CONF)
+power-par: $(POWER_CONF) sim-par
+power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
+redo-power-par: $(POWER_CONF)
+redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
+$(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)

vlsi/sim.mk

@@ -0,0 +1,38 @@
+.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF)
+# Update hammer top-level sim targets to include our generated sim configs
+redo-sim-rtl: $(SIM_CONF)
+redo-sim-rtl: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
+redo-sim-rtl-debug: $(SIM_DEBUG_CONF) redo-sim-rtl
+redo-sim-rtl-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+
+redo-sim-syn: $(SIM_CONF)
+redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
+redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn
+redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+
+redo-sim-par: $(SIM_CONF)
+redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
+redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par
+redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug
+redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
+
+sim-rtl: $(SIM_CONF)
+sim-rtl: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
+sim-rtl-debug: $(SIM_DEBUG_CONF) sim-rtl
+sim-rtl-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)
+
+sim-syn: $(SIM_CONF)
+sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
+sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn
+sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)
+
+sim-par: $(SIM_CONF)
+sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
+sim-par-debug: $(SIM_DEBUG_CONF) sim-par
+sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+sim-par-timing-debug: $(SIM_TIMING_CONF) sim-par-debug
+sim-par-timing-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
+$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)