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Support Chisel->SFC->Low FIRRTL->CFC->Verilog & Sim flow

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This commit is contained in:
joey0320
2022-12-23 11:24:35 -08:00
parent 4e4696eb3a
commit 13ece01450
1 changed files with 11 additions and 5 deletions
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16
common.mk
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@@ -146,13 +146,17 @@ FIRTOOL_TARGETS = \
$(FIRTOOL_FILELIST) \
$(FIRTOOL_BB_MODS_FILELIST)
$(info $$ENABLE_CUSTOM_FIRRTL_PASS $(ENABLE_CUSTOM_FIRRTL_PASS))
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
REPL_SEQ_MEM = none
# TOP_TARGETS = none
TOP_TARGETS = none
HARNESS_TARGETS = none
TRANSFORMS = barstools.tapeout.transforms.GenerateTop
else
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF)
TOP_TARGETS = $(TOP_SMEMS_CONF)
HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF)
HARNESS_TARGETS = $(HARNESS_SMEMS_CONF)
TRANSFORMS = barstools.tapeout.transforms.GenerateTopAndHarness
endif
@@ -185,13 +189,13 @@ $(CIRCT_TARGETS): firrtl_temp
@echo "" > /dev/null
# hack: lower to middle firrtl if Fixed types are found
$(TOP_TARGETS) $(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
$(HARNESS_TARGETS) $(TOP_TARGETS) $(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), middle, none))
else
$(eval SFC_LEVEL := low)
endif
$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTop,\
$(call run_scala_main,tapeout,$(TRANSFORMS),\
--no-dedup \
--output-file $(SFC_FIRRTL_BASENAME) \
--output-annotation-file $(SFC_ANNO_FILE) \
@@ -201,6 +205,7 @@ endif
--log-level $(FIRRTL_LOGLEVEL) \
--allow-unrecognized-annotations \
$(REPL_SEQ_MEM) \
$(HARNESS_CONF_FLAGS) \
-X $(SFC_LEVEL) \
$(EXTRA_FIRRTL_OPTIONS))
-mv $(SFC_FIRRTL_BASENAME).mid.fir $(SFC_FIRRTL_FILE)
@@ -226,7 +231,6 @@ endif
-o $(OUT_DIR) \
$(SFC_FIRRTL_FILE)
$(SED) -i 's/.*/& /' $(FIRTOOL_SMEMS_CONF) # need trailing space for SFC macrocompiler
cat $(TOP_SMEMS_CONF)
# DOC include end: FirrtlCompiler
$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) &: $(FIRTOOL_MODEL_HRCHY_JSON) $(FIRTOOL_FILELIST) $(FIRTOOL_BB_MODS_FILELIST)
@@ -243,6 +247,7 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
$(SED) -i 's/\.\///' $(BB_MODS_FILELIST)
sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
$(TOP_SMEMS_CONF) $(HARNESS_SMEMS_CONF) &: $(FIRTOOL_TOP_SMEMS_JSON) $(FIRTOOL_MODEL_SMEMS_JSON) $(FIRTOOL_SMEMS_CONF)
$(base_dir)/scripts/split-mems-conf.py \
--in-smems-conf $(FIRTOOL_SMEMS_CONF) \
@@ -250,6 +255,7 @@ $(TOP_SMEMS_CONF) $(HARNESS_SMEMS_CONF) &: $(FIRTOOL_TOP_SMEMS_JSON) $(FIRTOOL_M
--in-model-smems-json $(FIRTOOL_MODEL_SMEMS_JSON) \
--out-dut-smems-conf $(TOP_SMEMS_CONF) \
--out-model-smems-conf $(HARNESS_SMEMS_CONF)
endif
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
MACROCOMPILER_MODE ?= --mode synflops