RegInit is no longer in util (#14)

2017-03-14 23:24:31 -07:00
parent 4745d29912
commit 164bf2152c
1 changed files with 1 additions and 2 deletions
--- a/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
+++ b/tapeout/src/main/scala/transforms/clkgen/ClkDivider.scala
@@ -2,7 +2,6 @@ package barstools.tapeout.transforms.clkgen

 import chisel3.experimental.{withClockAndReset, withClock, withReset}
 import chisel3._
-import chisel3.util.RegInit
 import barstools.tapeout.transforms._
 import chisel3.util.HasBlackBoxInline

@@ -125,4 +124,4 @@ class SEClkDivider(divBy: Int, phases: Seq[Int], analogFile: String = "", syncRe
      }
      else throw new Exception("Clock divider Verilog file invalid!")
  }
-}
+}