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[skip ci] docs bump for review

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Harrison Liew
2019-09-25 15:11:41 -07:00
parent 29898bb677
commit 17578ddc93
6 changed files with 233 additions and 124 deletions
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189
docs/VLSI/HAMMER.rst
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@@ -4,7 +4,9 @@ Core HAMMER
`HAMMER <https://github.com/ucb-bar/hammer>`__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs.
HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
For more information, read the `HAMMER paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__.
For more information, read the `HAMMER paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__ and associated documentation.
Hammer implements a VLSI flow using the following high-level constructs:
Actions
-------
@@ -21,11 +23,18 @@ Hooks
Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration.
Configuration (Hammer IR)
=========================
To configure a Hammer flow, supply a set yaml or json configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions.
The current set of all available Hammer APIs is codified `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.
Tool Plugins
============
Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor Graphics plugins with permission from the respective CAD tool vendor.
The types of tools (by HAMMER names) supported currently include:
Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor plugins repositories with permission from the respective CAD tool vendor.
The types of tools (by Hammer names) supported currently include:
* synthesis
* par
@@ -34,46 +43,103 @@ The types of tools (by HAMMER names) supported currently include:
* sram_generator
* pcb
In order to configure your tool plugin of choice, you will need to set several configuration variables.
First, you should select which specific tool you want to use by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool.
For example ``vlsi.core.par_tool: "innovus"``.
You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifying the default values for any tool specific variables.
In addition you can also customize the version of the tools you use by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool.
Several configuration variables are needed to configure your tool plugin of choice.
The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support.
This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``.
First, select which tool to use for each action by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool, e.g. ``vlsi.core.par_tool: "innovus"``.
Then, point Hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
This directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tool.
This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``. The class should implement methods for all the tool's steps.
The ``defaults.yml`` file contains tool-specific configuration variables. The defaults may be overridden as necessary.
Technology Plugins
==================
Hammer supports separately managed plugins for different technologies. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``<tech_name>.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run. Refer to the ASAP7 plugin and associated documentation for more information.
Hammer supports separately managed technology plugins to satisfy NDAs. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``<tech_name>.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run.
In order to configure your technology of choice, you will need to set several configuration variables.
First, you need to choose the technology, for example ``vlsi.core.technology: asap7`` and point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir``.
Technology-specific options such as supplies, MMMC corners, metal layers, etc. will need to be matched to the technology in their respective ``vlsi.inputs...`` configurations.
The `ASAP7 plugin <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ is a good starting point for setting up a technology plugin. Refer to Hammer's documentation for the schema and setup instructions.
Configuration
=============
Several configuration variables are needed to configure your technology of choice.
To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs.
First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``.
You can see the current set of all available Hammer APIs `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.
Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user.
ASAP7 Tutorial
==============
The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is tested with the Cadence and Mentor tool plugins.
The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins.
Project Structure
-----------------
This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
* Makefile
* Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
* build
* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
* bwrc-env.yml
* An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment.
* example-vlsi
* Entry point to Hammer. Contains example placeholders for hooks.
* example.v
* Verilog wrapper around the accelerator and dummy hard macro.
* example.yml
* Hammer IR for this tutorial.
* extra_libraries
* Contains collateral for the dummy hard macro.
* generated-src
* All of the elaborated Chisel and FIRRTL.
* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
* Core, tool, tech repositories.
Prerequisites
-------------
* Python 3.4+
* numpy and gdspy packages
* Genus, Innovus, and Calibre licenses
* For ASAP7 specifically:
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball and do not extract it
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision
Initial Setup
-------------
Run ``./scripts/init-vlsi.sh TECH_HAME`` to pull the HAMMER & plugin submodules. Note that for technologies other than ASAP7, the tech submodule must be added in the ``vlsi`` folder first.
In the Chipyard root, run:
An example of tool environment configuration for BWRC affiliates is given in ``bwrc-env.yml``. Replace paths as necessary for your build environment.
.. code-block:: shell
Pull the HAMMER environment into the shell:
``./scripts/init-vlsi.sh asap7``
to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
::
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
@@ -81,42 +147,87 @@ Building the Design
-------------------
To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow:
::
export MACROCOMPILER_MODE=' --mode synflops'
.. code-block:: shell
export MACROCOMPILER_MODE='--mode synflops'
export CONFIG=Sha3RocketConfig
export VLSI_TOP=Sha3AccelwBB
make buildfile
Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead.
Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead.
For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed.
Running the VLSI Flow
---------------------
The configuration for this example is contained in ``example.yml`` and the entry script with placeholders for hooks is contained in ``example-vlsi``. Before continuing, ensure you have the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball downloaded (but not extracted) and point the ``technology.asap7.tarball_dir`` to the tarball directory.
To synthesize, type ``make syn``.
example-vlsi
^^^^^^^^^^^^
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods.
Post-synthesis results are in ``build/syn-rundir``. Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
example.yml
^^^^^^^^^^^
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
To place and route, type ``make par``.
First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK.
If successful, the resulting chip can be opened via ``./build/par-rundir/generated-scripts/open_chip``.
Synthesis
^^^^^^^^^
.. code-block:: shell
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. Compressed timing reports are found in ``build/par-rundir/timingReports``.
``make syn``
To run DRC & LVS, and view the results:
Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
Place-and-Route
^^^^^^^^^^^^^^^
.. code-block:: shell
``make par``
After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
DRC & LVS
^^^^^^^^^
To run DRC & LVS, and view the results in Calibre:
.. code-block:: shell
::
make drc
./build/drc-rundir/generated-scripts/view-drc
make lvs
./build/lvs-rundir/generated-scripts/view-lvs
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.
Advanced Usage
==============
Alternative RTL Flows
---------------------
The Make-based build system provided supports using HAMMER without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
.. code-block:: shell
::
export CUSTOM_VLOG=<your verilog files>
export VLSI_TOP=<your top module>
Manual Step Execution & Dependency Tracking
-------------------------------------------
It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``.
Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
.. code-block:: shell
make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
Simulation
----------
With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design.

33
vlsi/example.yml
View File

@@ -2,24 +2,16 @@
# Technology used is ASAP7
vlsi.core.technology: asap7
# Specify dir with ASAP7 tarball
technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL"
technology.asap7.tarball_dir: ""
vlsi.core.max_threads: 12
# General Hammer Inputs
vlsi.inputs.supplies.VDD: "0.7 V"
# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
vlsi.inputs.power_spec_type: "cpf"
# Specify the setup and hold corners for ASAP7
vlsi.inputs.mmmc_corners: [
{name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"},
{name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"}
]
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock", period: "1ns", uncertainty: "0.1ns"}
@@ -50,9 +42,10 @@ par.generate_power_straps_options:
power_utilization_M9: 1.0
# Placement Constraints
# For ASAP7, all numbers must be 4x larger than final GDS
vlsi.inputs.placement_constraints:
- path: "Sha3AccelwBB"
type: "toplevel"
type: toplevel
x: 0
y: 0
width: 300
@@ -63,12 +56,13 @@ vlsi.inputs.placement_constraints:
top: 0
bottom: 1.08 #must be at least this number
- path: "Sha3AccelwBB/dco"
type: "hardmacro"
x: 100
y: 100
width: 32
height: 32
orientation: "r0"
type: hardmacro
x: 108
y: 108
width: 128
height: 128
orientation: r0
top_layer: M9
# Pin placement constraints
vlsi.inputs.pin_mode: generated
@@ -116,7 +110,8 @@ par.inputs.physical_only_cells_list:
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
@@ -124,12 +119,12 @@ vlsi.core.sram_generator_tool_path_meta: "append"
vlsi.core.synthesis_tool: "genus"
vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
synthesis.genus.version: "181"
synthesis.genus.version: "1813"
# Innovus options
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "181"
par.innovus.version: "191"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options

BIN
vlsi/extra_libraries/dco/ExampleDCO.gds
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115
vlsi/extra_libraries/dco/ExampleDCO.lef
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@@ -3,26 +3,25 @@ BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO ExampleDCO
CLASS CORE ;
CLASS BLOCK ;
ORIGIN 0 0 ;
FOREIGN ExampleDCO 0 0 ;
SIZE 32.001 BY 32 ;
SIZE 128.0 BY 128.0 ;
SYMMETRY X Y ;
SITE coreSite ;
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M9 ;
RECT 8.24 31 8.4 32 ;
LAYER M7 ;
RECT 32.96 124.0 33.6 128.0 ;
END
END VDD
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER M9 ;
RECT 23.28 31 23.44 32 ;
LAYER M5 ;
RECT 93.12 124.0 93.76 128.0 ;
END
END VSS
PIN col_sel_b[13]
@@ -30,7 +29,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 28.32 1 28.416 ;
RECT 0.0 113.28 4.0 113.664 ;
END
END col_sel_b[13]
PIN col_sel_b[11]
@@ -38,7 +37,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 26.912 1 27.008 ;
RECT 0.0 107.648 4.0 108.032 ;
END
END col_sel_b[11]
PIN col_sel_b[5]
@@ -46,7 +45,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 22.688 1 22.784 ;
RECT 0.0 90.752 4.0 91.136 ;
END
END col_sel_b[5]
PIN col_sel_b[12]
@@ -54,7 +53,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 27.616 1 27.712 ;
RECT 0.0 110.464 4.0 110.848 ;
END
END col_sel_b[12]
PIN col_sel_b[10]
@@ -62,7 +61,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 26.208 1 26.304 ;
RECT 0.0 104.832 4.0 105.216 ;
END
END col_sel_b[10]
PIN col_sel_b[9]
@@ -70,7 +69,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 25.504 1 25.6 ;
RECT 0.0 102.016 4.0 102.4 ;
END
END col_sel_b[9]
PIN col_sel_b[8]
@@ -78,7 +77,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 24.8 1 24.896 ;
RECT 0.0 99.2 4.0 99.584 ;
END
END col_sel_b[8]
PIN col_sel_b[7]
@@ -86,7 +85,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 24.096 1 24.192 ;
RECT 0.0 96.384 4.0 96.768 ;
END
END col_sel_b[7]
PIN col_sel_b[6]
@@ -94,7 +93,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 23.392 1 23.488 ;
RECT 0.0 93.568 4.0 93.952 ;
END
END col_sel_b[6]
PIN col_sel_b[4]
@@ -102,7 +101,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 21.984 1 22.08 ;
RECT 0.0 87.936 4.0 88.32 ;
END
END col_sel_b[4]
PIN col_sel_b[3]
@@ -110,7 +109,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 21.28 1 21.376 ;
RECT 0.0 85.12 4.0 85.504 ;
END
END col_sel_b[3]
PIN col_sel_b[2]
@@ -118,7 +117,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 20.576 1 20.672 ;
RECT 0.0 82.304 4.0 82.688 ;
END
END col_sel_b[2]
PIN col_sel_b[1]
@@ -126,7 +125,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 19.872 1 19.968 ;
RECT 0.0 79.488 4.0 79.872 ;
END
END col_sel_b[1]
PIN col_sel_b[0]
@@ -134,7 +133,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 19.168 1 19.264 ;
RECT 0.0 76.672 4.0 77.056 ;
END
END col_sel_b[0]
PIN row_sel_b[14]
@@ -142,7 +141,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 17.76 1 17.856 ;
RECT 0.0 71.04 4.0 71.424 ;
END
END row_sel_b[14]
PIN row_sel_b[13]
@@ -150,7 +149,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 17.056 1 17.152 ;
RECT 0.0 68.224 4.0 68.608 ;
END
END row_sel_b[13]
PIN row_sel_b[12]
@@ -158,7 +157,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 16.352 1 16.448 ;
RECT 0.0 65.408 4.0 65.792 ;
END
END row_sel_b[12]
PIN row_sel_b[11]
@@ -166,7 +165,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 15.648 1 15.744 ;
RECT 0.0 62.592 4.0 62.976 ;
END
END row_sel_b[11]
PIN row_sel_b[10]
@@ -174,7 +173,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 14.944 1 15.04 ;
RECT 0.0 59.776 4.0 60.16 ;
END
END row_sel_b[10]
PIN row_sel_b[9]
@@ -182,7 +181,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 14.24 1 14.336 ;
RECT 0.0 56.96 4.0 57.344 ;
END
END row_sel_b[9]
PIN row_sel_b[8]
@@ -190,7 +189,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 13.536 1 13.632 ;
RECT 0.0 54.144 4.0 54.528 ;
END
END row_sel_b[8]
PIN row_sel_b[7]
@@ -198,7 +197,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 12.832 1 12.928 ;
RECT 0.0 51.328 4.0 51.712 ;
END
END row_sel_b[7]
PIN row_sel_b[6]
@@ -206,7 +205,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 12.128 1 12.224 ;
RECT 0.0 48.512 4.0 48.896 ;
END
END row_sel_b[6]
PIN row_sel_b[5]
@@ -214,7 +213,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 11.424 1 11.52 ;
RECT 0.0 45.696 4.0 46.08 ;
END
END row_sel_b[5]
PIN row_sel_b[4]
@@ -222,7 +221,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 10.72 1 10.816 ;
RECT 0.0 42.88 4.0 43.264 ;
END
END row_sel_b[4]
PIN row_sel_b[3]
@@ -230,7 +229,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 10.016 1 10.112 ;
RECT 0.0 40.064 4.0 40.448 ;
END
END row_sel_b[3]
PIN row_sel_b[2]
@@ -238,7 +237,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 9.312 1 9.408 ;
RECT 0.0 37.248 4.0 37.632 ;
END
END row_sel_b[2]
PIN row_sel_b[1]
@@ -246,7 +245,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 8.608 1 8.704 ;
RECT 0.0 34.432 4.0 34.816 ;
END
END row_sel_b[1]
PIN row_sel_b[0]
@@ -254,7 +253,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 7.904 1 8 ;
RECT 0.0 31.616 4.0 32.0 ;
END
END row_sel_b[0]
PIN code_regulator[7]
@@ -262,7 +261,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 7.2 1 7.296 ;
RECT 0.0 28.8 4.0 29.184 ;
END
END code_regulator[7]
PIN code_regulator[6]
@@ -270,7 +269,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 6.496 1 6.592 ;
RECT 0.0 25.984 4.0 26.368 ;
END
END code_regulator[6]
PIN code_regulator[5]
@@ -278,7 +277,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 5.792 1 5.888 ;
RECT 0.0 23.168 4.0 23.552 ;
END
END code_regulator[5]
PIN code_regulator[4]
@@ -286,7 +285,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 5.088 1 5.184 ;
RECT 0.0 20.352 4.0 20.736 ;
END
END code_regulator[4]
PIN code_regulator[3]
@@ -294,7 +293,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 4.384 1 4.48 ;
RECT 0.0 17.536 4.0 17.92 ;
END
END code_regulator[3]
PIN code_regulator[2]
@@ -302,7 +301,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 3.68 1 3.776 ;
RECT 0.0 14.72 4.0 15.104 ;
END
END code_regulator[2]
PIN code_regulator[1]
@@ -310,7 +309,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 2.976 1 3.072 ;
RECT 0.0 11.904 4.0 12.288 ;
END
END code_regulator[1]
PIN code_regulator[0]
@@ -318,7 +317,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 2.272 1 2.368 ;
RECT 0.0 9.088 4.0 9.472 ;
END
END code_regulator[0]
PIN row_sel_b[15]
@@ -326,7 +325,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 18.464 1 18.56 ;
RECT 0.0 73.856 4.0 74.24 ;
END
END row_sel_b[15]
PIN dither
@@ -334,7 +333,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0 1.568 1 1.664 ;
RECT 0.0 6.272 4.0 6.656 ;
END
END dither
PIN sleep_b
@@ -342,7 +341,7 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M5 ;
RECT 2.448 0 2.544 1 ;
RECT 9.792 0.0 10.176 4.0 ;
END
END sleep_b
PIN clock
@@ -350,26 +349,30 @@ MACRO ExampleDCO
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 31 17.716 32 17.812 ;
RECT 124.0 70.864 128.0 71.248 ;
END
END clock
OBS
LAYER M1 ;
RECT 1 1 31 31 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M2 ;
RECT 1 1 31 31 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M3 ;
RECT 1 1 31 31 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M4 ;
RECT 1 1 31 31 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M5 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M6 ;
RECT 1 1 31 31 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M7 ;
RECT 1 1 31 31 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M8 ;
RECT 1 1 31 31 ;
RECT 0.0 0.0 128.0 128.0 ;
LAYER M9 ;
RECT 1 1 31 31 ;
RECT 0.0 0.0 128.0 128.0 ;
LAYER Pad ;
RECT 0.0 0.0 128.0 128.0 ;
END
END ExampleDCO

10
vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib
View File

@@ -90,7 +90,7 @@ library (ExampleDCO_PVT_0P63V_100C) {
bus_type : bus_13_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
pin ( col_sel_b[13:0] ) {
related_power_pin : VDD;
@@ -102,7 +102,7 @@ library (ExampleDCO_PVT_0P63V_100C) {
bus_type : bus_15_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
pin ( row_sel_b[15:0] ) {
related_power_pin : VDD;
@@ -114,7 +114,7 @@ library (ExampleDCO_PVT_0P63V_100C) {
bus_type : bus_7_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
pin ( code_regulator[7:0] ) {
related_power_pin : VDD;
@@ -125,7 +125,7 @@ library (ExampleDCO_PVT_0P63V_100C) {
pin (dither) {
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
@@ -133,7 +133,7 @@ library (ExampleDCO_PVT_0P63V_100C) {
pin (sleep_b) {
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}

10
vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib
View File

@@ -90,7 +90,7 @@ library (ExampleDCO_PVT_0P77V_0C) {
bus_type : bus_13_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
pin ( col_sel_b[13:0] ) {
related_power_pin : VDD;
@@ -102,7 +102,7 @@ library (ExampleDCO_PVT_0P77V_0C) {
bus_type : bus_15_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
pin ( row_sel_b[15:0] ) {
related_power_pin : VDD;
@@ -114,7 +114,7 @@ library (ExampleDCO_PVT_0P77V_0C) {
bus_type : bus_7_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
pin ( code_regulator[7:0] ) {
related_power_pin : VDD;
@@ -125,7 +125,7 @@ library (ExampleDCO_PVT_0P77V_0C) {
pin (dither) {
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
@@ -133,7 +133,7 @@ library (ExampleDCO_PVT_0P77V_0C) {
pin (sleep_b) {
direction : input;
capacitance : 0.006;
max_transition : 0.039999999999999994;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}