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Update testchipip with source-synchronous serdes

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This commit is contained in:
Jerry Zhao
2023-12-21 20:33:24 -08:00
parent cfd555ee94
commit 194d4462f9
10 changed files with 60 additions and 41 deletions
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2
fpga/src/main/scala/arty100t/Configs.scala
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@@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config(
class BringupArty100TConfig extends Config(
new WithArty100TSerialTLToGPIO ++
new WithArty100TTweaks(freqMHz = 50) ++
new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++
new chipyard.ChipBringupHostConfig)

8
fpga/src/main/scala/arty100t/HarnessBinders.scala
View File

@@ -53,8 +53,8 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
harnessIO match {
case io: DecoupledSerialIO => {
val clkIO = io match {
case io: LocallySyncSerialIO => IOPin(io.clock_out)
case io: ExternallySyncSerialIO => IOPin(io.clock_in)
case io: InternalSyncSerialIO => IOPin(io.clock_out)
case io: ExternalSyncSerialIO => IOPin(io.clock_in)
}
val packagePinsWithPackageIOs = Seq(
("G13", clkIO),
@@ -78,10 +78,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
// Don't add IOB to the clock, if its an input
io match {
case io: LocallySyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
case io: ExternallySyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
}