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Bump firesim for CI

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This commit is contained in:
David Biancolin
2020-03-24 10:41:17 -07:00
parent 7a17323bed
commit 1b7158835a
2 changed files with 36 additions and 35 deletions
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69
generators/firechip/src/test/scala/ScalaTestSuite.scala
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@@ -151,37 +151,38 @@ class RocketMulticlockF1Tests extends FireSimTestSuite(
"FireSimQuadRocketMulticlockConfig",
"WithSynthAsserts_BaseF1Config")
abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
lazy val generatorArgs = GeneratorArgs(
midasFlowKind = "midas",
targetDir = "generated-src",
topModuleProject = "firesim.firesim",
topModuleClass = "FireSimTraceGen",
targetConfigProject = "firesim.firesim",
targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
platformConfigProject = "firesim.firesim",
platformConfigs = platformConfig)
// From HasFireSimGeneratorUtilities
// For the firesim utilities to use the same directory as the test suite
override lazy val testDir = genDir
// From TestSuiteCommon
val targetTuple = generatorArgs.tupleName
val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
it should "pass" in {
assert(make("fsim-tracegen") == 0)
}
}
class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
"DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
class FireSimL2TraceGenTest extends FireSimTraceGenTest(
"DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")
// Jerry broke these -- damn it Jerry.
//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
//
// lazy val generatorArgs = GeneratorArgs(
// midasFlowKind = "midas",
// targetDir = "generated-src",
// topModuleProject = "firesim.firesim",
// topModuleClass = "FireSimTraceGen",
// targetConfigProject = "firesim.firesim",
// targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
// platformConfigProject = "firesim.firesim",
// platformConfigs = platformConfig)
//
// // From HasFireSimGeneratorUtilities
// // For the firesim utilities to use the same directory as the test suite
// override lazy val testDir = genDir
//
// // From TestSuiteCommon
// val targetTuple = generatorArgs.tupleName
// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
// s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
//
// it should "pass" in {
// assert(make("fsim-tracegen") == 0)
// }
//}
//
//class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
//
//class FireSimL2TraceGenTest extends FireSimTraceGenTest(
// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")

2
sims/firesim

Submodule sims/firesim updated: ce0d05a10a...552a9764a1