Update Sky130-OpenROAD-Tutorial.rst

docs/VLSI/Sky130-OpenROAD-Tutorial.rst

@@ -72,18 +72,6 @@ Pull the Hammer environment into the shell:
     export HAMMER_HOME=$PWD/hammer
     source $HAMMER_HOME/sourceme.sh
 
-Building the Design
---------------------
-To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
-
-.. code-block:: shell
-
-    make buildfile tech_name=sky130 CONFIG=TinyRocketConfig
-
-The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
-
-For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
-
 Running the VLSI Flow
 ---------------------
 
@@ -101,8 +89,46 @@ First, set ``technology.sky130.<sky130A, sky130_nda, openram_lib>`` to the absol
 for details about the PDK setup.
 
 
+Generating SRAMs
+----------------
+To map the generic memory macros in the generarted Verilog to the SRAMs in your technology process, run the following command:
+
+.. code-block:: shell
+
+    make srams tech_name=sky130 CONFIG=TinyRocketConfig
+
+Generating Verilog
+------------------
+To elaborate the ``TinyRocketConfig`` from Chisel to Verilog, run:
+
+.. code-block:: shell
+
+    make verilog tech_name=sky130 CONFIG=TinyRocketConfig
+
+The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``.
+
+Note that in the generated Verilog, there are generic memory macros for the various memory components (dcache, icache, tag array, PTW). 
+This is the same Verilog that is generated for RTL simulations in the ``~chipyard/sims/verilator`` directory, see ` :ref:`Simulation/Software-RTL-Simulation:sw-rtl-sim-intro` for directions on how to run these simulations.
+
+Building the Design
+^^^^^^^^^^^^^^^^^^^
+To set up all prerequisites for the build system to push the design and SRAM macros through the flow:
+
+.. code-block:: shell
+
+    make buildfile tech_name=sky130 CONFIG=TinyRocketConfig
+
+For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
+
+
+example-openroad.yml
+^^^^^^^^^^^^^^^^^^^^
+This contains the Hammer configuration for the OpenROAD tool flow. It selects tools for the SRAM "compiler" (already specified in ``example-sky130.yml``), synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen). For the remaining commands, we will need to specify this file as the tool configuration to hammer via the ``TOOLS_CONF`` Makefile variable.
+
+
 Synthesis
 ^^^^^^^^^
+
 .. code-block:: shell
 
     make syn tech_name=sky130 TOOLS_CONF=example-openroad.yml CONFIG=TinyRocketConfig