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Merge branch 'graphics' of https://github.com/hansungk/chipyard into graphics

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This commit is contained in:
Richard Yan
2023-10-13 13:26:48 -07:00
parent 3a6c3c51b4 304ea362d0
commit 246c1e81f0
70 changed files with 2535 additions and 2520 deletions
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3
.github/scripts/defaults.sh vendored
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@@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
grouping["group-fpga"]="arty vcu118 vc707"
grouping["group-fpga"]="arty vcu118 vc707 arty100t"
# key value store to get the build strings
declare -A mapping
@@ -81,3 +81,4 @@ mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig
mapping["arty"]="SUB_PROJECT=arty verilog"
mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
mapping["vc707"]="SUB_PROJECT=vc707 verilog"
mapping["arty100t"]="SUB_PROJECT=arty100t verilog"

10
.github/workflows/chipyard-full-flow.yml vendored
View File

@@ -143,6 +143,7 @@ jobs:
echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> tutorial.yml
echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml
echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
echo "drc.klayout.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml
echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
echo "" >> tutorial.yml
echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
@@ -157,12 +158,13 @@ jobs:
export VLSI_TOP=RocketTile
make buildfile
make syn
# NOTE: commenting out for now bc this times out - need to debug why
# openroad freezes during some write commands after detailed route
# so need to stop the flow & run last step separately
make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
make drc
make lvs
# make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
# make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
# make drc
# make lvs
cleanup:

696
.github/workflows/chipyard-run-tests-gpu.yml vendored Normal file
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@@ -0,0 +1,696 @@
name: chipyard-ci-gpu
on:
push:
branches:
- graphics
defaults:
run:
shell: bash -leo pipefail {0}
env:
tools-cache-version: v17
CI_DIR: ${{ secrets.BUILDDIR }}
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
conda-env-name-no-time: cy-${{ github.run_id }}
workflow-timestamp: ${{ github.event.pull_request.updated_at }}
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
jobs:
cancel-prior-workflows:
name: cancel-prior-workflows
runs-on: self-hosted
steps:
- name: Cancel Previous Runs
uses: styfle/cancel-workflow-action@0.11.0
with:
access_token: ${{ github.token }}
# Set up a set of boolean conditions to control which branches of the CI
# workflow will execute This is based off the conditional job execution
# example here: https://github.com/dorny/paths-filter#examples
change-filters:
name: filter-jobs-on-changes
runs-on: self-hosted
# Queried by downstream jobs to determine if they should run.
outputs:
needs-rtl: ${{ steps.filter.outputs.all_count != steps.filter.outputs.skip-rtl_count }}
steps:
- uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- uses: dorny/paths-filter@v2
id: filter
with:
filters: |
all:
- '**'
# If any of the files changed match, do a doc build
docs: &docs-filter
- 'docs/**'
- '.readthedocs.yml'
# If all files match to this filter, skip the main ci pipeline
skip-rtl:
- *docs-filter
- '**/*.md'
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'
create-conda-env:
name: create-conda-env
needs: [change-filters, cancel-prior-workflows]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Cleanup conda
uses: ./.github/actions/cleanup-conda
- name: Create conda env
uses: ./.github/actions/create-conda-env
# Sentinel job to simplify how we specify which that basic setup is complete
#
# When adding new prep jobs, please add them to `needs` below
setup-complete:
name: setup-complete
needs: [create-conda-env]
runs-on: self-hosted
steps:
- name: Set up complete
run: echo Set up is complete!
##########################################################################
prepare-chipyard-cores:
name: prepare-chipyard-cores
needs: setup-complete
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build RTL on self-hosted
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-cores"
prepare-chipyard-accels:
name: prepare-chipyard-accels
needs: setup-complete
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build RTL on self-hosted
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-accels"
prepare-chipyard-tracegen:
name: prepare-chipyard-tracegen
needs: setup-complete
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build RTL on self-hosted
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-tracegen"
prepare-chipyard-other:
name: prepare-chipyard-other
needs: setup-complete
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build RTL on self-hosted
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-other"
##########################################################################
chipyard-spike-gemmini-run-tests:
name: chipyard-spike-gemmini-run-tests
needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build Gemmini FireMarshal
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force
cd ${{ github.workspace }} && source ./scripts/fix-open-files.sh
git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh
cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json
- name: Running Gemmini FireMarshal smoke test
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json
chipyard-rocket-run-tests:
name: chipyard-rocket-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-rocket"
chipyard-prefetchers-run-tests:
name: chipyard-prefetchers-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-prefetchers"
chipyard-hetero-run-tests:
name: chipyard-hetero-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-hetero"
chipyard-boom-run-tests:
name: chipyard-boom-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-boom"
chipyard-shuttle-run-tests:
name: chipyard-shuttle-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-shuttle"
chipyard-cva6-run-tests:
name: chipyard-cva6-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-cva6"
chipyard-ibex-run-tests:
name: chipyard-ibex-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-ibex"
chipyard-sodor-run-tests:
name: chipyard-sodor-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-sodor"
chipyard-spike-run-tests:
name: chipyard-spike-run-tests
needs: prepare-chipyard-cores
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-spike"
chipyard-sha3-run-tests:
name: chipyard-sha3-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-sha3"
chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-gemmini"
chipyard-manymmioaccels-run-tests:
name: chipyard-manymmioaccels-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-manymmioaccels"
# chipyard-nvdla-run-tests:
# name: chipyard-nvdla-run-tests
# needs: prepare-chipyard-accels
# runs-on: self-hosted
# steps:
# - name: Delete old checkout
# run: |
# ls -alh .
# rm -rf ${{ github.workspace }}/* || true
# rm -rf ${{ github.workspace }}/.* || true
# ls -alh .
# - name: Checkout
# uses: actions/checkout@v3
# - name: Git workaround
# uses: ./.github/actions/git-workaround
# - name: Create conda env
# uses: ./.github/actions/create-conda-env
# - name: Run tests
# uses: ./.github/actions/run-tests
# with:
# group-key: "group-accels"
# project-key: "chipyard-nvdla"
chipyard-mempress-run-tests:
name: chipyard-mempress-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-mempress"
tracegen-boom-run-tests:
name: tracegen-boom-run-tests
needs: prepare-chipyard-tracegen
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-tracegen"
project-key: "tracegen-boom"
tracegen-run-tests:
name: tracegen-run-tests
needs: prepare-chipyard-tracegen
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-tracegen"
project-key: "tracegen"
icenet-run-tests:
name: icenet-run-tests
needs: prepare-chipyard-other
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-other"
project-key: "icenet"
testchipip-run-tests:
name: testchipip-run-tests
needs: prepare-chipyard-other
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-other"
project-key: "testchipip"
rocketchip-run-tests:
name: rocketchip-run-tests
needs: prepare-chipyard-other
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run amba tests
uses: ./.github/actions/run-tests
with:
group-key: "group-other"
project-key: "rocketchip-amba"
# Below tests segfault with verilator, work fine in VCS
# - name: Run tlsimple tests
# uses: ./.github/actions/run-tests
# with:
# group-key: "group-other"
# project-key: "rocketchip-tlsimple"
# - name: Run tlwidth tests
# uses: ./.github/actions/run-tests
# with:
# group-key: "group-other"
# project-key: "rocketchip-tlwidth"
# - name: Run tlxbar tests
# uses: ./.github/actions/run-tests
# with:
# group-key: "group-other"
# project-key: "rocketchip-tlxbar"
# Sentinel job to simplify how we specify which checks need to pass in branch
# protection and in Mergify
#
# When adding new top level jobs, please add them to `needs` below
all_tests_passed:
name: "all tests passed"
needs: [chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
chipyard-boom-run-tests,
chipyard-shuttle-run-tests,
chipyard-cva6-run-tests,
chipyard-ibex-run-tests,
chipyard-sodor-run-tests,
chipyard-sha3-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
chipyard-prefetchers-run-tests,
chipyard-mempress-run-tests,
tracegen-boom-run-tests,
tracegen-run-tests,
icenet-run-tests,
testchipip-run-tests,
rocketchip-run-tests,
]
runs-on: self-hosted
steps:
- run: echo Success!

222
.github/workflows/chipyard-run-tests.yml vendored
View File

@@ -62,122 +62,6 @@ jobs:
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'
commit-on-master-check:
name: commit-on-master-check
needs: change-filters
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: ubuntu-latest
container:
image: ucbbar/chipyard-ci-image:3f9150
options: --entrypoint /bin/bash
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check commits of each submodule
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
.github/scripts/check-commit.sh
tutorial-setup-check:
name: tutorial-setup-check
needs: change-filters
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: ubuntu-latest
container:
image: ucbbar/chipyard-ci-image:3f9150
options: --entrypoint /bin/bash
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check that the tutorial-setup patches apply
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
scripts/tutorial-setup.sh
documentation-check:
name: documentation-check
needs: change-filters
runs-on: ubuntu-latest
container:
image: ucbbar/chipyard-ci-image:3f9150
options: --entrypoint /bin/bash
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check that documentation builds with no warnings/errors
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
make -C docs html
- name: Show error log from sphinx if failed
if: ${{ failure() }}
run: cat /tmp/sphinx-err*.log
build-extra-tests:
name: build-extra-tests
needs: [change-filters]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: ubuntu-latest
container:
image: ucbbar/chipyard-ci-image:3f9150
options: --entrypoint /bin/bash
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Generate keys
id: genkey
run: |
echo "extra-tests-cache-key=extra-tests-${{ github.sha }}" >> $GITHUB_OUTPUT
- uses: actions/cache@v3
id: build-extra-tools-cache
with:
path: extra-tests-install
key: ${{ steps.genkey.outputs.extra-tests-cache-key }}
restore-keys: ${{ steps.genkey.outputs.extra-tests-cache-key }}
- name: Build extra tests
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
.github/scripts/build-extra-tests.sh
create-conda-env-jktgz:
name: create-conda-env-jktgz
needs: [change-filters, cancel-prior-workflows]
@@ -225,7 +109,7 @@ jobs:
# When adding new prep jobs, please add them to `needs` below
setup-complete:
name: setup-complete
needs: [create-conda-env-jktgz, create-conda-env-jktqos, build-extra-tests]
needs: [create-conda-env-jktgz, create-conda-env-jktqos]
runs-on: ubuntu-latest
steps:
- name: Set up complete
@@ -233,6 +117,110 @@ jobs:
##########################################################################
commit-on-master-check:
name: commit-on-master-check
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check commits of each submodule
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
.github/scripts/check-commit.sh
tutorial-setup-check:
name: tutorial-setup-check
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check that the tutorial-setup patches apply
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
scripts/tutorial-setup.sh
documentation-check:
name: documentation-check
needs: [setup-complete]
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check that documentation builds with no warnings/errors
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
make -C docs html
- name: Show error log from sphinx if failed
if: ${{ failure() }}
run: cat /tmp/sphinx-err*.log
build-extra-tests:
name: build-extra-tests
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Generate keys
id: genkey
run: |
echo "extra-tests-cache-key=extra-tests-${{ github.sha }}" >> $GITHUB_OUTPUT
- uses: actions/cache@v3
id: build-extra-tools-cache
with:
path: extra-tests-install
key: ${{ steps.genkey.outputs.extra-tests-cache-key }}
restore-keys: ${{ steps.genkey.outputs.extra-tests-cache-key }}
- name: Build extra tests
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
.github/scripts/build-extra-tests.sh
prepare-chipyard-cores:
name: prepare-chipyard-cores
needs: setup-complete

3
.gitmodules vendored
View File

@@ -64,9 +64,6 @@
[submodule "software/nvdla-workload"]
path = software/nvdla-workload
url = https://github.com/ucb-bar/nvdla-workload.git
[submodule "tools/dromajo/dromajo-src"]
path = tools/dromajo/dromajo-src
url = https://github.com/riscv-boom/dromajo.git
[submodule "generators/riscv-sodor"]
path = generators/riscv-sodor
url = https://github.com/ucb-bar/riscv-sodor.git

1
common.mk
View File

@@ -68,7 +68,6 @@ include $(base_dir)/generators/cva6/cva6.mk
include $(base_dir)/generators/ibex/ibex.mk
include $(base_dir)/generators/tracegen/tracegen.mk
include $(base_dir)/generators/nvdla/nvdla.mk
include $(base_dir)/tools/dromajo/dromajo.mk
include $(base_dir)/tools/torture.mk
#########################################################################################

3
conda-reqs/chipyard.yaml
View File

@@ -29,7 +29,6 @@ dependencies:
- conda-gcc-specs
- binutils
- dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo
- firtool==1.30.0 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
# misc
@@ -103,7 +102,7 @@ dependencies:
- sty
- open_pdks.sky130a
- pip:
- hammer-vlsi[asap7]==1.1.1
- hammer-vlsi[asap7]==1.1.2
# doc requirements
- sphinx

1466
conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml generated
View File

File diff suppressed because it is too large Load Diff

1432
conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml generated
View File

File diff suppressed because it is too large Load Diff

1
docs/Advanced-Concepts/Architectural-Checkpoints.rst
View File

@@ -36,4 +36,3 @@ The target config should also match the architectural configuration of however s
cd sims/vcs
make CONFIG=dmiRocketConfig run-binary LOADARCH=../../hello.riscv.0x80000000.1000.loadarch

25
docs/Advanced-Concepts/Chip-Communication.rst
View File

@@ -183,28 +183,21 @@ This new setup (shown below) is a typical Chipyard test chip setup:
Simulation Setup of the Example Test Chip
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To test this type of configuration (TSI/memory transactions over the serial-link), most of the same TSI collateral
would be used.
The main difference is that the TileLink-to-AXI converters and simulated AXI memory resides on the other side of the
serial-link.
The standard test-chip bringup procedure tethers the chip to a FPGA config with serialized tilelink.
.. image:: ../_static/images/chip-bringup-simulation.png
.. note::
Here the simulated AXI memory and the converters can be in a different clock domain in the test harness
than the reference clock of the DUT.
For example, the DUT can be clocked at 3.2GHz while the simulated AXI memory can be clocked at 1GHz.
This functionality is done in the harness binder that instantiates the TSI collateral, TL-to-AXI converters,
and simulated AXI memory.
See :ref:`Advanced-Concepts/Harness-Clocks:Creating Clocks in the Test Harness` on how to generate a clock
in a harness binder.
The entire bringup procedure can be simulated using the Multi-ChipTop simulation feature, where
one ``ChipTop`` is the design-to-be-taped-out, while the other is the FPGA bringup design.
This type of simulation setup is done in the following multi-clock configuration:
This system can be generated and simulated with the following example configuration, which marries
a ``ChipLikeRocketConfig`` (the design to be taped-out) with the ``ChipBringupHostConfig`` (the FPGA
bringup design).
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/ChipConfigs.scala
:language: scala
:start-after: DOC include start: MulticlockAXIOverSerialConfig
:end-before: DOC include end: MulticlockAXIOverSerialConfig
:start-after: DOC include start: TetheredChipLikeRocketConfig
:end-before: DOC include end: TetheredChipLikeRocketConfig
Softcore-driven Bringup Setup of the Example Test Chip after Tapeout
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

33
docs/Advanced-Concepts/Debugging-BOOM.rst
View File

@@ -1,33 +0,0 @@
Debugging BOOM
======================
In addition to the default debugging techniques specified in :ref:`Advanced-Concepts/Debugging-RTL:Debugging RTL`,
single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Tools/Dromajo:Dromajo`)
to verify functionality.
.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators.
.. warning:: Dromajo currently only works in VCS simulation and FireSim.
Setting up Dromajo Co-simulation
--------------------------------------
Dromajo co-simulation is setup to work when three config fragments are added to a BOOM config.
* A ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled.
* A ``chipyard.iobinders.WithTraceIOPunchthrough`` config fragment must be added to add the ``TraceIO`` to the ``ChipTop``
* A ``chipyard.harness.WithSimDromajoBridge`` config fragment must be added to instantiate a Dromajo cosimulator in the ``TestHarness`` and connect it to the ``ChipTop``'s ``TraceIO``
Once all config fragments are added Dromajo should be enabled.
To build/run Dromajo with a BOOM design, run your configuration the following make commands:
.. code-block:: shell
# build the default Dromajo BOOM config without waveform dumps
# replace "DromajoBoomConfig" with your particular config
make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1
# run a simulation with Dromajo
make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY=<YOUR-BIN> run-binary

2
docs/Advanced-Concepts/Debugging-RTL.rst
View File

@@ -100,6 +100,6 @@ You can find the overnight options in `overnight/src/main/scala/main.scala` in t
Firesim Debugging
---------------------------
Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim
Chisel printfs, asserts, Cospike co-simulation, and waveform generation are also available in FireSim
FPGA-accelerated simulation. See the FireSim
`documentation <https://docs.fires.im/en/latest/>`__ for more detail.

1
docs/Advanced-Concepts/Harness-Clocks.rst
View File

@@ -21,4 +21,3 @@ Take the following example:
:end-before: DOC include end: HarnessClockInstantiatorEx
Here you can see the ``th.harnessClockInstantiator`` is used to request a clock and reset at ``memFreq`` frequency.

1
docs/Advanced-Concepts/index.rst
View File

@@ -11,7 +11,6 @@ They expect you to know about Chisel, Parameters, configs, etc.
Top-Testharness
Chip-Communication
Debugging-RTL
Debugging-BOOM
Resources
CDEs
Harness-Clocks

4
docs/Chipyard-Basics/Chipyard-Components.rst
View File

@@ -86,10 +86,6 @@ Tools
**Dsptools**
A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
**Dromajo**
A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technologies.
See :ref:`Tools/Dromajo:Dromajo` for more information.
Toolchains
-------------------------------------------

2
docs/Chipyard-Basics/Initial-Repo-Setup.rst
View File

@@ -9,7 +9,7 @@ Chipyard is developed and tested on Linux-based systems.
.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed;
it is also recommended to install the RISC-V toolchain from ``brew``.
.. Warning:: Working under Windows is not recommended.
.. Warning:: If using Windows, it is recommended that you use `Windows Subsystem for Linux <https://learn.microsoft.com/en-us/windows/wsl/> (WSL)`.
Running on AWS EC2 with FireSim
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2
docs/Customization/Custom-Chisel.rst
View File

@@ -52,7 +52,7 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file.
You can then import the classes defined in the submodule in a new project if
you add it as a dependency. For instance, if you want to use this code in
the ``chipyard`` project, add your project to the list of sub-projects in the
the ``chipyard`` project, add your project to the list of sub-projects in the
`.dependsOn()` for `lazy val chipyard`. The original code may change over time, but it
should look something like this:

1
docs/Customization/RoCC-Accelerators.rst
View File

@@ -112,4 +112,3 @@ For instance, if we wanted to add the previously defined accelerator and route c
new RocketConfig)
To add RoCC instructions in your program, use the RoCC C macros provided in ``tests/rocc.h``. You can find examples in the files ``tests/accum.c`` and ``charcount.c``.

18
docs/Generators/SiFive-Generators.rst
View File

@@ -16,7 +16,7 @@ Peripheral Devices Overview
``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC.
When adding a top-level IO, you should also be aware of whether it interacts with the test-harness.
@@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example:
General Purpose I/Os (GPIO) Device
----------------------------------
GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
GPIO main features
@@ -67,7 +67,7 @@ Including GPIO in the SoC
// Set up Memory Devices
// ==================================
// ...
// Peripheral section
new chipyard.config.WithGPIO(address = 0x10010000, width = 32) ++
@@ -115,7 +115,7 @@ Including UART in the SoC
// Set up Memory Devices
// ==================================
// ...
// Peripheral section
new chipyard.config.WithUART(address = 0x10020000, baudrate = 115200) ++
@@ -125,7 +125,7 @@ Including UART in the SoC
Inter-Integrated Circuit (I2C) Interface Device
-------------------------------------------------
I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
I2C main features
@@ -158,7 +158,7 @@ Including I2C in the SoC
// Set up Memory Devices
// ==================================
// ...
// Peripheral section
new chipyard.config.WithI2C(address = 0x10040000) ++
@@ -169,9 +169,9 @@ Including I2C in the SoC
Serial Peripheral Interface (SPI) Device
-------------------------------------------------
SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
SPI main features
@@ -208,7 +208,7 @@ Including SPI in the SoC
// Set up Memory Devices
// ==================================
// ...
// Peripheral section
new chipyard.config.WithSPI(address = 0x10031000) ++

6
docs/Simulation/Software-RTL-Simulation.rst
View File

@@ -177,8 +177,8 @@ A special target that automatically generates the waveform file for a specific t
For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
If you have Synopsys licenses, we recommend using the DVE waveform viewer.
For a VCS simulation, this will generate an fsdb file that can be loaded to fsdb-supported waveform viewers.
If you have Synopsys licenses, we recommend using the Verdi waveform viewer.
Visualizing Chipyard SoCs
--------------------------
@@ -187,7 +187,7 @@ During verilog creation, a graphml file is emitted that will allow you to visual
To view the graph, first download a viewer such as `yEd <https://www.yworks.com/products/yed/>`__.
The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer.
The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer.
To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings.
.. _sw-sim-verilator-opts:

22
docs/Tools/Dromajo.rst
View File

@@ -1,22 +0,0 @@
Dromajo
===============================
`Dromajo <https://github.com/chipsalliance/dromajo/>`__ is a RV64GC functional simulator designed for co-simulation.
To use it as a co-simulator, it requires you to pass the committed trace of instructions coming from the core into the tool.
Within Chipyard, this is done by connecting to the `TracePort`` signals that are piped to the top level of the DUT.
While the Rocket core does have a `TracePort`, it does not provide the committed write data that Dromajo requires.
Thus, Dromajo uses the `ExtendedTracePort` only probided by BOOM (BOOM is the only core that supports Dromajo co-simulation).
An example of a divergence and Dromajo's printout is shown below.
.. code-block:: shell
[error] EMU PC ffffffe001055d84, DUT PC ffffffe001055d84
[error] EMU INSN 14102973, DUT INSN 14102973
[error] EMU WDATA 00000000000220d6, DUT WDATA 00000000000220d4
[error] EMU MSTATUS a000000a0, DUT MSTATUS 00000000
[error] DUT pending exception -1 pending interrupt -1
Dromajo shows the divergence compared to simulation (PC, inst, inst-bits, write data, etc) and also provides the register state on failure.
It is useful to catch bugs that affect architectural state before a simulation hangs or crashes.
To use Dromajo with BOOM, refer to :ref:`Advanced-Concepts/Debugging-RTL:Debugging RTL` section on Dromajo.

1
docs/Tools/index.rst
View File

@@ -13,4 +13,3 @@ The following pages will introduce them, and how we can use them in order to gen
Treadle
Dsptools
Barstools
Dromajo

4
docs/VLSI/Advanced-Usage.rst
View File

@@ -8,7 +8,7 @@ Hammer Development and Upgrades
If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
.. code-block:: shell
pip install -e <path/to/hammer>
To bump specific plugins to their latest commits and install them, you can use the upgrade script from the Chipyard root directory, with arguments for match patterns for the plugin names:
@@ -120,7 +120,7 @@ The given example in ``UPFInputs`` corresponds to a dual-core Rocket config with
To run the flow:
.. code-block:: shell
cd chipyard/vlsi
make verilog ASPECTS=chipyard.upf.ChipTopUPFAspect

6
docs/VLSI/Sky130-Commercial-Tutorial.rst
View File

@@ -48,7 +48,7 @@ Prerequisites
* Python 3.9+
* Genus, Innovus, Voltus, VCS, and Calibre licenses
* Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
* `Sram22 Sky130 SRAM macros <https://github.com/rahulk29/sram22_sky130_macros>`__
* `Sram22 Sky130 SRAM macros <https://github.com/rahulk29/sram22_sky130_macros>`__
* These SRAM macros were generated using the `Sram22 SRAM generator <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
@@ -75,7 +75,7 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
We will summarize a few files in this directory that will be important for the rest of the tutorial.
.. code-block:: shell
@@ -123,7 +123,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
and (2) the mapping of memory instances in the design to SRAM macros;
all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
Note that the files in ``generated-src`` vary for each tool/technology flow.
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.

54
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
View File

@@ -46,16 +46,17 @@ Prerequisites
-------------
* Python 3.9+
* OpenROAD flow tools:
* OpenROAD flow tools (NOTE: tutorial may break with different tool versions):
* Yosys (synthesis), install `using conda <https://anaconda.org/litex-hub/yosys>`__ or `from source <https://yosyshq.net/yosys/download.html>`__
* OpenROAD (place-and-route), install `using conda <https://anaconda.org/litex-hub/openroad>`__ (note that GUI is disabled in conda package) or `from source <https://openroad.readthedocs.io/en/latest/main/README.html#install-dependencies>`__
* KLayout (DEF to GDSII conversion), install `using conda <https://anaconda.org/litex-hub/klayout>`__ or `from source <https://www.klayout.de/build.html>`__
* Magic (DRC), , install `using conda <https://anaconda.org/litex-hub/magic>`__ or `from source <http://www.opencircuitdesign.com/magic/install.html>`__
* NetGen (LVS), , install `using conda <https://anaconda.org/litex-hub/netgen>`__ or `from source <http://www.opencircuitdesign.com/netgen/install.html>`__
* **Yosys 0.27+3** (synthesis), install `using conda <https://anaconda.org/litex-hub/yosys>`__ or `from source <https://yosyshq.net/yosys/download.html>`__
* **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda <https://anaconda.org/litex-hub/openroad>`__ (note that GUI is disabled in conda package) or
`from source <https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/docs/user/Build.md>`__ (git hash: 0264023b6c2a8ae803b8d440478d657387277d93)
* **KLayout 0.28.5** (DEF to GDSII conversion, DRC), install `using conda <https://anaconda.org/litex-hub/klayout>`__ or `from source <https://www.klayout.de/build.html>`__
* **Magic 8.3.376** (DRC), install `using conda <https://anaconda.org/litex-hub/magic>`__ or `from source <http://www.opencircuitdesign.com/magic/install.html>`__
* **NetGen 1.5.250** (LVS), install `using conda <https://anaconda.org/litex-hub/netgen>`__ or `from source <http://www.opencircuitdesign.com/netgen/install.html>`__
* Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
* `Sram22 Sky130 SRAM macros <https://github.com/rahulk29/sram22_sky130_macros>`__
* `Sram22 Sky130 SRAM macros <https://github.com/rahulk29/sram22_sky130_macros>`__
* These SRAM macros were generated using the `Sram22 SRAM generator <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
@@ -67,6 +68,10 @@ Note that we create a new conda environment for each tool because some of them h
.. code-block:: shell
# channel settings so openroad/klayout install properly
conda config --set channel_priority true
conda config --add channels defaults
# download all files for Sky130A PDK
conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
# clone the SRAM22 Sky130 SRAM macros
@@ -78,6 +83,10 @@ Note that we create a new conda environment for each tool because some of them h
conda create -c litex-hub --prefix ~/.conda-klayout klayout=0.28.5_98_g87e2def28
conda create -c litex-hub --prefix ~/.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
# revert conda settings
conda config --set channel_priority strict
conda config --remove channels defaults
Initial Setup
-------------
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
@@ -86,10 +95,10 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
./scripts/init-vlsi.sh sky130 openroad
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder,
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder,
and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
We will summarize a few files in this directory that will be important for the rest of the tutorial.
.. code-block:: shell
@@ -118,7 +127,7 @@ Add the following YAML keys to the top of this file to specify the location of t
example-openroad.yml
^^^^^^^^^^^^^^^^^^^^
This contains the Hammer configuration for the OpenROAD tool flow.
It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen).
It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (KLayout or Magic), and LVS (NetGen).
Add the following YAML keys to the top of this file to specify the locations of the tool binaries.
Note that this is not required if the tools are already on your PATH.
@@ -129,7 +138,8 @@ Note that this is not required if the tools are already on your PATH.
# tool binary paths
synthesis.yosys.yosys_bin: ~/.conda-yosys/bin/yosys
par.openroad.openroad_bin: ~/.conda-openroad/bin/openroad
par.openroad.klayout_bin: ~/.conda-klayout/bin/klayout
par.openroad.klayout_bin: ~/.conda-klayout/bin/klayout # binary that OpenROAD calls for final GDS writeout
drc.klayout.klayout_bin: ~/.conda-klayout/bin/klayout # binary that runs for DRC step
drc.magic.magic_bin: ~/.conda-signoff/bin/magic
lvs.netgen.netgen_bin: ~/.conda-signoff/bin/netgen
@@ -151,7 +161,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
and (2) the mapping of memory instances in the design to SRAM macros;
all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
Note that the files in ``generated-src`` vary for each tool/technology flow.
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
@@ -188,7 +198,7 @@ Place-and-Route
make par tutorial=sky130-openroad
Note that sometimes OpenROAD freezes on commands following the ``detailed_route`` step,
so for now we recomment running place-and-route until the ``extraction`` step,
so for now we recomment running place-and-route until the ``extraction`` step,
then re-starting the flow at this step. See the :ref:`VLSI/Sky130-OpenROAD-Tutorial:VLSI Flow Control` documentation
below for how to break up the flow into these steps.
@@ -237,10 +247,14 @@ DRC & LVS
As a note, this tutorial has been run extensively through commercial signoff tools,
thus the open-source signoff flow is not stable or guaranteed to produce useful results.
We welcome any contributions to improving both our `Magic tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/drc/magic>`__
We welcome any contributions to improving our `KLayout tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/drc/klayout>`__,
`Magic tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/drc/magic>`__,
and `Netgen tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/lvs/netgen>`__.
To run DRC & LVS in Magic & Netgen, respectively:
We recommend KLayout for DRC to produce readable results, but Magic may be selected in ``example-openroad.yml``
by uncommenting the line ``vlsi.core.drc_tool: "hammer.drc.magic"``.
To run DRC & LVS and view the results:
.. code-block:: shell
@@ -259,7 +273,13 @@ Note that in ``sky130-openroad.yml`` we have set the following YAML keys:
These keys cause the Hammer plugin to only generate all necessary scripts, without executing them with the respective tool.
This is because Magic and Netgen, as of the writing of this tutorial, do not have a database format that may be loaded interactively,
so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks,
which is done by the ``generated-scripts/view_[drc|lvs]`` scripts.
which is done by the ``generated-scripts/view_[drc|lvs]`` scripts. This is not the case for KLayout, which does have a loadable database format.
Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are
from special rules relating to Sky130 SRAMs, which have been verified separately. In the future the KLayout tool plugin should blackbox these
SRAM macros by default, but this feature does not exist yet.
.. image:: ../_static/images/vlsi-openroad-klayout-drc.png
VLSI Flow Control
@@ -273,7 +293,7 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
# the following two commands are equivalent because the extraction
# the following two commands are equivalent because the extraction
# step immediately precedes the write_design step
make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"

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2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: 1bdd436287...7d0b79f855

1
fpga/src/main/scala/arty100t/Harness.scala
View File

@@ -54,6 +54,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
override lazy val module = new HarnessLikeImpl
class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
all_leds.foreach(_ := DontCare)
clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock

2
fpga/src/main/scala/vcu118/Configs.scala
View File

@@ -77,6 +77,8 @@ class BoomVCU118Config extends Config(
)
class WithFPGAFrequency(fMHz: Double) extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
new chipyard.config.WithMemoryBusFrequency(fMHz)
)

2
generators/boom

Submodule generators/boom updated: 247ed4903d...96da674bc9

508
generators/chipyard/src/main/resources/csrc/cospike.cc
View File

@@ -1,508 +0,0 @@
#include <cstdint>
#include <vector>
#include <string>
#include <riscv/sim.h>
#include <riscv/mmu.h>
#include <riscv/encoding.h>
#include <vpi_user.h>
#include <svdpi.h>
#include <sstream>
#include <set>
#include <sys/types.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <unistd.h>
#include <sys/syscall.h>
#include <fcntl.h>
#if __has_include ("cospike_dtm.h")
#define COSPIKE_DTM
#include "testchip_dtm.h"
extern testchip_dtm_t* dtm;
bool spike_loadarch_done = false;
#endif
#if __has_include ("mm.h")
#define COSPIKE_SIMDRAM
#include "mm.h"
extern std::map<long long int, backing_data_t> backing_mem_data;
#endif
#define CLINT_BASE (0x2000000)
#define CLINT_SIZE (0x10000)
#define UART_BASE (0x54000000)
#define UART_SIZE (0x1000)
#define PLIC_BASE (0xc000000)
#define PLIC_SIZE (0x4000000)
#define COSPIKE_PRINTF(...) { \
printf(__VA_ARGS__); \
fprintf(stderr, __VA_ARGS__); \
}
typedef struct system_info_t {
std::string isa;
int vlen;
int pmpregions;
uint64_t mem0_base;
uint64_t mem0_size;
int nharts;
std::vector<char> bootrom;
std::string priv;
};
class read_override_device_t : public abstract_device_t {
public:
read_override_device_t(std::string n, reg_t sz) : was_read_from(false), size(sz), name(n) { };
virtual bool load(reg_t addr, size_t len, uint8_t* bytes) override {
if (addr + len > size) return false;
COSPIKE_PRINTF("Read from device %s at %lx\n", name.c_str(), addr);
was_read_from = true;
return true;
}
virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) override {
COSPIKE_PRINTF("Store to device %s at %lx\n", name.c_str(), addr);
return (addr + len <= size);
}
bool was_read_from;
private:
reg_t size;
std::string name;
};
system_info_t* info = NULL;
sim_t* sim = NULL;
bool cospike_debug;
reg_t tohost_addr = 0;
reg_t fromhost_addr = 0;
reg_t cospike_timeout = 0;
std::set<reg_t> magic_addrs;
cfg_t* cfg;
std::vector<std::shared_ptr<read_override_device_t>> read_override_devices;
static std::vector<std::pair<reg_t, abstract_mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
{
std::vector<std::pair<reg_t, abstract_mem_t*>> mems;
mems.reserve(layout.size());
for (const auto &cfg : layout) {
mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size())));
}
return mems;
}
extern "C" void cospike_set_sysinfo(char* isa, int vlen, char* priv, int pmpregions,
long long int mem0_base, long long int mem0_size,
int nharts,
char* bootrom
) {
if (!info) {
info = new system_info_t;
// technically the targets aren't zicntr compliant, but they implement the zicntr registers
info->isa = std::string(isa) + "_zicntr";
info->vlen = vlen;
info->priv = std::string(priv);
info->pmpregions = pmpregions;
info->mem0_base = mem0_base;
info->mem0_size = mem0_size;
info->nharts = nharts;
std::stringstream ss(bootrom);
std::string s;
while (ss >> s) {
info->bootrom.push_back(std::stoi(s));
}
}
}
extern "C" void cospike_cosim(long long int cycle,
long long int hartid,
int has_wdata,
int valid,
long long int iaddr,
unsigned long int insn,
int raise_exception,
int raise_interrupt,
unsigned long long int cause,
unsigned long long int wdata,
int priv)
{
assert(info);
if (unlikely(!sim)) {
COSPIKE_PRINTF("Configuring spike cosim\n");
std::vector<mem_cfg_t> mem_cfg;
std::vector<size_t> hartids;
mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size));
for (int i = 0; i < info->nharts; i++)
hartids.push_back(i);
std::string visa = "vlen:" + std::to_string(info->vlen ? info->vlen : 128) + ",elen:64";
cfg = new cfg_t(std::make_pair(0, 0),
nullptr,
info->isa.c_str(),
info->priv.c_str(),
visa.c_str(),
false,
endianness_little,
info->pmpregions,
mem_cfg,
hartids,
false,
0
);
std::vector<std::pair<reg_t, abstract_mem_t*>> mems = make_mems(cfg->mem_layout());
size_t default_boot_rom_size = 0x10000;
size_t default_boot_rom_addr = 0x10000;
assert(info->bootrom.size() < default_boot_rom_size);
info->bootrom.resize(default_boot_rom_size);
std::shared_ptr<rom_device_t> boot_rom = std::make_shared<rom_device_t>(info->bootrom);
std::shared_ptr<mem_t> boot_addr_reg = std::make_shared<mem_t>(0x1000);
uint64_t default_boot_addr = 0x80000000;
boot_addr_reg.get()->store(0, 8, (const uint8_t*)(&default_boot_addr));
std::shared_ptr<read_override_device_t> clint = std::make_shared<read_override_device_t>("clint", CLINT_SIZE);
std::shared_ptr<read_override_device_t> uart = std::make_shared<read_override_device_t>("uart", UART_SIZE);
std::shared_ptr<read_override_device_t> plic = std::make_shared<read_override_device_t>("plic", PLIC_SIZE);
read_override_devices.push_back(clint);
read_override_devices.push_back(uart);
read_override_devices.push_back(plic);
std::vector<std::pair<reg_t, std::shared_ptr<abstract_device_t>>> devices;
// The device map is hardcoded here for now
devices.push_back(std::pair(0x4000, boot_addr_reg));
devices.push_back(std::pair(default_boot_rom_addr, boot_rom));
devices.push_back(std::pair(CLINT_BASE, clint));
devices.push_back(std::pair(UART_BASE, uart));
devices.push_back(std::pair(PLIC_BASE, plic));
s_vpi_vlog_info vinfo;
if (!vpi_get_vlog_info(&vinfo))
abort();
std::vector<std::string> htif_args;
bool in_permissive = false;
cospike_debug = false;
for (int i = 1; i < vinfo.argc; i++) {
std::string arg(vinfo.argv[i]);
if (arg == "+permissive") {
in_permissive = true;
} else if (arg == "+permissive-off") {
in_permissive = false;
} else if (arg == "+cospike_debug" || arg == "+cospike-debug") {
cospike_debug = true;
} else if (arg.find("+cospike-timeout=") == 0) {
cospike_timeout = strtoull(arg.substr(17).c_str(), 0, 10);
} else if (!in_permissive) {
htif_args.push_back(arg);
}
}
debug_module_config_t dm_config = {
.progbufsize = 2,
.max_sba_data_width = 0,
.require_authentication = false,
.abstract_rti = 0,
.support_hasel = true,
.support_abstract_csr_access = true,
.support_abstract_fpr_access = true,
.support_haltgroups = true,
.support_impebreak = true
};
COSPIKE_PRINTF("isa string: %s\n", info->isa.c_str());
COSPIKE_PRINTF("htif args: ");
for (int i = 0; i < htif_args.size(); i++) {
COSPIKE_PRINTF("%s", htif_args[i].c_str());
}
COSPIKE_PRINTF("\n");
std::vector<const device_factory_t*> plugin_device_factories;
sim = new sim_t(cfg, false,
mems,
plugin_device_factories,
htif_args,
dm_config,
nullptr,
false,
nullptr,
false,
nullptr
);
for (auto &it : devices)
sim->add_device(it.first, it.second);
#ifdef COSPIKE_SIMDRAM
// match sim_t's backing memory with the SimDRAM memory
bus_t temp_mem_bus;
for (auto& pair : mems) temp_mem_bus.add_device(pair.first, pair.second);
for (auto& pair : backing_mem_data) {
size_t base = pair.first;
size_t size = pair.second.size;
COSPIKE_PRINTF("Matching spike memory initial state for region %lx-%lx\n", base, base + size);
if (!temp_mem_bus.store(base, size, pair.second.data)) {
COSPIKE_PRINTF("Error, unable to match memory at address %lx\n", base);
abort();
}
}
#endif
sim->configure_log(true, true);
for (int i = 0; i < info->nharts; i++) {
// Use our own reset vector
sim->get_core(hartid)->get_state()->pc = 0x10040;
// Set MMU to support up to sv39, as our normal hw configs do
sim->get_core(hartid)->set_impl(IMPL_MMU_SV48, false);
sim->get_core(hartid)->set_impl(IMPL_MMU_SV57, false);
// HACKS: Our processor's don't implement zicntr fully, they don't provide time
sim->get_core(hartid)->get_state()->csrmap.erase(CSR_TIME);
}
sim->set_debug(cospike_debug);
sim->set_histogram(true);
sim->set_procs_debug(cospike_debug);
COSPIKE_PRINTF("Setting up htif for spike cosim\n");
((htif_t*)sim)->start();
COSPIKE_PRINTF("Spike cosim started\n");
tohost_addr = ((htif_t*)sim)->get_tohost_addr();
fromhost_addr = ((htif_t*)sim)->get_fromhost_addr();
COSPIKE_PRINTF("Tohost : %lx\n", tohost_addr);
COSPIKE_PRINTF("Fromhost: %lx\n", fromhost_addr);
COSPIKE_PRINTF("BootROM base : %lx\n", default_boot_rom_addr);
COSPIKE_PRINTF("BootROM size : %lx\n", boot_rom->contents().size());
COSPIKE_PRINTF("Memory base : %lx\n", info->mem0_base);
COSPIKE_PRINTF("Memory size : %lx\n", info->mem0_size);
}
if (priv & 0x4) { // debug
return;
}
if (cospike_timeout && cycle > cospike_timeout) {
if (sim) {
COSPIKE_PRINTF("Cospike reached timeout cycles = %ld, terminating\n", cospike_timeout);
delete sim;
}
exit(0);
}
processor_t* p = sim->get_core(hartid);
state_t* s = p->get_state();
#ifdef COSPIKE_DTM
if (dtm && dtm->loadarch_done && !spike_loadarch_done) {
COSPIKE_PRINTF("Restoring spike state from testchip_dtm loadarch\n");
// copy the loadarch state into the cosim
loadarch_state_t &ls = dtm->loadarch_state[hartid];
s->pc = ls.pc;
s->prv = ls.prv;
s->csrmap[CSR_MSTATUS]->write(s->csrmap[CSR_MSTATUS]->read() | MSTATUS_VS | MSTATUS_XS | MSTATUS_FS);
#define RESTORE(CSRID, csr) s->csrmap[CSRID]->write(ls.csr);
RESTORE(CSR_FCSR , fcsr);
RESTORE(CSR_VSTART , vstart);
RESTORE(CSR_VXSAT , vxsat);
RESTORE(CSR_VXRM , vxrm);
RESTORE(CSR_VCSR , vcsr);
RESTORE(CSR_VTYPE , vtype);
RESTORE(CSR_STVEC , stvec);
RESTORE(CSR_SSCRATCH , sscratch);
RESTORE(CSR_SEPC , sepc);
RESTORE(CSR_SCAUSE , scause);
RESTORE(CSR_STVAL , stval);
RESTORE(CSR_SATP , satp);
RESTORE(CSR_MSTATUS , mstatus);
RESTORE(CSR_MEDELEG , medeleg);
RESTORE(CSR_MIDELEG , mideleg);
RESTORE(CSR_MIE , mie);
RESTORE(CSR_MTVEC , mtvec);
RESTORE(CSR_MSCRATCH , mscratch);
RESTORE(CSR_MEPC , mepc);
RESTORE(CSR_MCAUSE , mcause);
RESTORE(CSR_MTVAL , mtval);
RESTORE(CSR_MIP , mip);
RESTORE(CSR_MCYCLE , mcycle);
RESTORE(CSR_MINSTRET , minstret);
if (ls.VLEN != p->VU.VLEN) {
COSPIKE_PRINTF("VLEN mismatch loadarch: $d != spike: $d\n", ls.VLEN, p->VU.VLEN);
abort();
}
if (ls.ELEN != p->VU.ELEN) {
COSPIKE_PRINTF("ELEN mismatch loadarch: $d != spike: $d\n", ls.ELEN, p->VU.ELEN);
abort();
}
for (size_t i = 0; i < 32; i++) {
s->XPR.write(i, ls.XPR[i]);
s->FPR.write(i, { (uint64_t)ls.FPR[i], (uint64_t)-1 });
memcpy(p->VU.reg_file + i * ls.VLEN / 8, ls.VPR[i], ls.VLEN / 8);
}
spike_loadarch_done = true;
p->clear_waiting_for_interrupt();
}
#endif
uint64_t s_pc = s->pc;
uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF;
bool ssip_interrupt = interrupt_cause == 0x1;
bool msip_interrupt = interrupt_cause == 0x3;
bool stip_interrupt = interrupt_cause == 0x5;
bool mtip_interrupt = interrupt_cause == 0x7;
bool debug_interrupt = interrupt_cause == 0xe;
if (raise_interrupt) {
COSPIKE_PRINTF("%d interrupt %lx\n", cycle, cause);
if (ssip_interrupt || stip_interrupt) {
// do nothing
} else if (msip_interrupt) {
s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP);
} else if (mtip_interrupt) {
s->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP);
} else if (debug_interrupt) {
return;
} else {
COSPIKE_PRINTF("Unknown interrupt %lx\n", interrupt_cause);
abort();
}
}
if (raise_exception)
COSPIKE_PRINTF("%d exception %lx\n", cycle, cause);
if (valid) {
p->clear_waiting_for_interrupt();
COSPIKE_PRINTF("%d Cosim: %lx", cycle, iaddr);
// if (has_wdata) {
// COSPIKE_PRINTF(" s: %lx", wdata);
// }
COSPIKE_PRINTF("\n");
}
if (valid || raise_interrupt || raise_exception) {
p->clear_waiting_for_interrupt();
for (auto& e : read_override_devices) e.get()->was_read_from = false;
p->step(1);
if (unlikely(cospike_debug)) {
COSPIKE_PRINTF("spike pc is %lx\n", s->pc);
COSPIKE_PRINTF("spike mstatus is %lx\n", s->mstatus->read());
COSPIKE_PRINTF("spike mip is %lx\n", s->mip->read());
COSPIKE_PRINTF("spike mie is %lx\n", s->mie->read());
COSPIKE_PRINTF("spike wfi state is %d\n", p->is_waiting_for_interrupt());
}
}
if (valid && !raise_exception) {
if (s_pc != iaddr) {
COSPIKE_PRINTF("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr);
if (unlikely(cospike_debug)) {
COSPIKE_PRINTF("spike mstatus is %lx\n", s->mstatus->read());
COSPIKE_PRINTF("spike mcause is %lx\n", s->mcause->read());
COSPIKE_PRINTF("spike mtval is %lx\n" , s->mtval->read());
COSPIKE_PRINTF("spike mtinst is %lx\n", s->mtinst->read());
}
exit(1);
}
auto& mem_write = s->log_mem_write;
auto& log = s->log_reg_write;
auto& mem_read = s->log_mem_read;
for (auto memwrite : mem_write) {
reg_t waddr = std::get<0>(memwrite);
uint64_t w_data = std::get<1>(memwrite);
if ((waddr == CLINT_BASE + 4*hartid) && w_data == 0) {
s->mip->backdoor_write_with_mask(MIP_MSIP, 0);
}
if ((waddr == CLINT_BASE + 0x4000 + 4*hartid)) {
s->mip->backdoor_write_with_mask(MIP_MTIP, 0);
}
// Try to remember magic_mem addrs, and ignore these in the future
if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) {
COSPIKE_PRINTF("Probable magic mem %lx\n", w_data);
magic_addrs.insert(w_data);
}
}
bool scalar_wb = false;
bool vector_wb = false;
uint32_t vector_cnt = 0;
std::vector<reg_t> vector_rds;
for (auto &regwrite : log) {
//TODO: scaling to multi issue reads?
reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]);
int rd = regwrite.first >> 4;
int type = regwrite.first & 0xf;
// 0 => int
// 1 => fp
// 2 => vec
// 3 => vec hint
// 4 => csr
bool device_read = false;
for (auto& e : read_override_devices) if (e.get()->was_read_from) device_read = true;
bool lr_read = ((insn & MASK_LR_D) == MATCH_LR_D) || ((insn & MASK_LR_W) == MATCH_LR_W);
bool sc_read = ((insn & MASK_SC_D) == MATCH_SC_D) || ((insn & MASK_SC_W) == MATCH_SC_W);
bool ignore_read = sc_read || (!mem_read.empty() &&
(magic_addrs.count(mem_read_addr) ||
device_read ||
lr_read ||
(tohost_addr && mem_read_addr == tohost_addr) ||
(fromhost_addr && mem_read_addr == fromhost_addr)));
//COSPIKE_PRINTF("register write type %d\n", type);
// check the type is compliant with writeback first
if ((type == 0 || type == 1))
scalar_wb = true;
if (type == 2) {
vector_rds.push_back(rd);
vector_wb = true;
}
if (type == 3) continue;
if ((rd != 0 && type == 0) || type == 1) {
// Override reads from some CSRs
uint64_t csr_addr = (insn >> 20) & 0xfff;
bool csr_read = (insn & 0x7f) == 0x73;
if (csr_read)
COSPIKE_PRINTF("CSR read %lx\n", csr_addr);
if (csr_read && ((csr_addr == 0x301) || // misa
(csr_addr == 0x306) || // mcounteren
(csr_addr == 0xf13) || // mimpid
(csr_addr == 0xf12) || // marchid
(csr_addr == 0xf11) || // mvendorid
(csr_addr == 0xb00) || // mcycle
(csr_addr == 0xb02) || // minstret
(csr_addr == 0xc00) || // cycle
(csr_addr == 0xc01) || // time
(csr_addr == 0xc02) || // instret
(csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers
(csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr
)) {
COSPIKE_PRINTF("CSR override\n");
s->XPR.write(rd, wdata);
} else if (ignore_read) {
// Don't check reads from tohost, reads from magic memory, or reads
// from clint Technically this could be buggy because log_mem_read
// only reports vaddrs, but no software ever should access
// tohost/fromhost/clint with vaddrs anyways
COSPIKE_PRINTF("Read override %lx = %lx\n", mem_read_addr, wdata);
s->XPR.write(rd, wdata);
} else if (wdata != regwrite.second.v[0]) {
COSPIKE_PRINTF("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd,
regwrite.second.v[0], wdata);
exit(1);
}
}
// TODO FIX: Rocketchip TracedInstruction.wdata should be Valid(UInt)
// if (scalar_wb ^ has_wdata) {
// COSPIKE_PRINTF("Scalar wdata behavior divergence between spike and DUT\n");
// exit(-1);
// }
}
for (auto &a : vector_rds) {
COSPIKE_PRINTF("vector writeback to v%d\n", a);
}
}
}

0
generators/chipyard/src/main/resources/csrc/cospike_dtm.h
View File

81
generators/chipyard/src/main/resources/vsrc/cospike.v
View File

@@ -1,81 +0,0 @@
import "DPI-C" function void cospike_set_sysinfo(
input string isa,
input int vlen,
input string priv,
input int pmpregions,
input longint mem0_base,
input longint mem0_size,
input int nharts,
input string bootrom
);
import "DPI-C" function void cospike_cosim(input longint cycle,
input longint hartid,
input bit has_wdata,
input bit valid,
input longint iaddr,
input int insn,
input bit raise_exception,
input bit raise_interrupt,
input longint cause,
input longint wdata,
input int priv
);
module SpikeCosim #(
parameter ISA,
parameter PRIV,
parameter VLEN,
parameter PMPREGIONS,
parameter MEM0_BASE,
parameter MEM0_SIZE,
parameter NHARTS,
parameter BOOTROM) (
input clock,
input reset,
input [63:0] cycle,
input [63:0] hartid,
input trace_0_valid,
input [63:0] trace_0_iaddr,
input [31:0] trace_0_insn,
input trace_0_exception,
input trace_0_interrupt,
input [63:0] trace_0_cause,
input trace_0_has_wdata,
input [63:0] trace_0_wdata,
input [2:0] trace_0_priv,
input trace_1_valid,
input [63:0] trace_1_iaddr,
input [31:0] trace_1_insn,
input trace_1_exception,
input trace_1_interrupt,
input [63:0] trace_1_cause,
input trace_1_has_wdata,
input [63:0] trace_1_wdata,
input [2:0] trace_1_priv
);
initial begin
cospike_set_sysinfo(ISA, VLEN, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
end;
always @(posedge clock) begin
if (!reset) begin
if (trace_0_valid || trace_0_exception || trace_0_cause) begin
cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr,
trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause,
trace_0_wdata, trace_0_priv);
end
if (trace_1_valid || trace_1_exception || trace_1_cause) begin
cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr,
trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause,
trace_1_wdata, trace_1_priv);
end
end
end
endmodule; // CospikeCosim

6
generators/chipyard/src/main/resources/vsrc/spiketile.v
View File

@@ -286,10 +286,10 @@ module SpikeBlackBox #(
wire __tcm_d_ready;
bit __tcm_d_valid;
longint __tcm_d_data;
reg __tcm_d_valid_reg;
reg [63:0] __tcm_d_data_reg;
always @(posedge clock) begin
@@ -429,7 +429,7 @@ module SpikeBlackBox #(
__tcm_d_valid_reg <= __tcm_d_valid;
__tcm_d_data_reg <= __tcm_d_data;
end
end // always @ (posedge clock)
assign insns_retired = __insns_retired_reg;

93
generators/chipyard/src/main/scala/Cospike.scala
View File

@@ -1,93 +0,0 @@
package chipyard
import chisel3._
import chisel3.experimental.{IntParam, StringParam, IO}
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import testchipip.TileTraceIO
case class SpikeCosimConfig(
isa: String,
vlen: Int,
priv: String,
pmpregions: Int,
mem0_base: BigInt,
mem0_size: BigInt,
nharts: Int,
bootrom: String,
has_dtm: Boolean
)
class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map(
"ISA" -> StringParam(cfg.isa),
"VLEN" -> IntParam(cfg.vlen),
"PRIV" -> StringParam(cfg.priv),
"PMPREGIONS" -> IntParam(cfg.pmpregions),
"MEM0_BASE" -> IntParam(cfg.mem0_base),
"MEM0_SIZE" -> IntParam(cfg.mem0_size),
"NHARTS" -> IntParam(cfg.nharts),
"BOOTROM" -> StringParam(cfg.bootrom)
)) with HasBlackBoxResource
{
addResource("/csrc/cospike.cc")
addResource("/vsrc/cospike.v")
if (cfg.has_dtm) addResource("/csrc/cospike_dtm.h")
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val cycle = Input(UInt(64.W))
val hartid = Input(UInt(64.W))
val trace = Input(Vec(2, new Bundle {
val valid = Bool()
val iaddr = UInt(64.W)
val insn = UInt(32.W)
val exception = Bool()
val interrupt = Bool()
val cause = UInt(64.W)
val has_wdata = Bool()
val wdata = UInt(64.W)
val priv = UInt(3.W)
}))
})
}
object SpikeCosim
{
def apply(trace: TileTraceIO, hartid: Int, cfg: SpikeCosimConfig) = {
val cosim = Module(new SpikeCosim(cfg))
val cycle = withClockAndReset(trace.clock, trace.reset) {
val r = RegInit(0.U(64.W))
r := r + 1.U
r
}
cosim.io.clock := trace.clock
cosim.io.reset := trace.reset
require(trace.numInsns <= 2)
cosim.io.cycle := cycle
cosim.io.trace.map(t => {
t := DontCare
t.valid := false.B
})
cosim.io.hartid := hartid.U
for (i <- 0 until trace.numInsns) {
val insn = trace.trace.insns(i)
cosim.io.trace(i).valid := insn.valid
val signed = Wire(SInt(64.W))
signed := insn.iaddr.asSInt
cosim.io.trace(i).iaddr := signed.asUInt
cosim.io.trace(i).insn := insn.insn
cosim.io.trace(i).exception := insn.exception
cosim.io.trace(i).interrupt := insn.interrupt
cosim.io.trace(i).cause := insn.cause
cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B
cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U)
cosim.io.trace(i).priv := insn.priv
}
}
}

5
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
@@ -124,7 +124,4 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasTilesModuleImp
{
// Generate C header with relevant information for Dromajo
// This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts(InSubsystem)
}

1
generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
View File

@@ -91,4 +91,3 @@ class SimplePllConfiguration(
}
def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1
}

1
generators/chipyard/src/main/scala/clocking/TileClockGater.scala
View File

@@ -45,4 +45,3 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
}): _*)
}
}

8
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -41,13 +41,6 @@ class LoopbackNICLargeBoomConfig extends Config(
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class DromajoBoomConfig extends Config(
new chipyard.harness.WithSimDromajoBridge ++ // attach Dromajo
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNSmallBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomCosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
@@ -67,4 +60,3 @@ class dmiMediumBoomCosimConfig extends Config(
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)

20
generators/chipyard/src/main/scala/config/ChipConfigs.scala
View File

@@ -12,27 +12,26 @@ class ChipLikeRocketConfig extends Config(
//==================================
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
// NOTE: This only simulates properly in VCS
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach SimDRAM to serial-tl port
//==================================
// Set up tiles
//==================================
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++ // Add async crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile
//==================================
// Set up I/O
//==================================
new testchipip.WithSerialTLWidth(4) ++
new testchipip.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO
new testchipip.WithSerialTLBackingMemory ++ // Configure the off-chip memory accessible over serial-tl as backing memory
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//==================================
// Set up buses
//==================================
new testchipip.WithOffchipBusClient(MBUS) ++
new testchipip.WithOffchipBus ++
new testchipip.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
new testchipip.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory
//==================================
// Set up clock./reset
@@ -90,12 +89,13 @@ class ChipBringupHostConfig extends Config(
// Base is the no-cores config
new chipyard.NoCoresConfig)
// DOC include start: TetheredChipLikeRocketConfig
class TetheredChipLikeRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute freqs for sims in the harness
new chipyard.harness.WithMultiChipSerialTL(0, 1) ++ // connect the serial-tl ports of the chips together
new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++ // ChipTop0 is the design-to-be-taped-out
new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig)) // ChipTop1 is the bringup design
// DOC include end: TetheredChipLikeRocketConfig
// Verilator does not initialize some of the async-reset reset-synchronizer
// flops properly, so this config disables them.

1
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -92,4 +92,3 @@ class UARTTSIRocketConfig extends Config(
new chipyard.config.WithPeripheryBusFrequency(10) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig)

39
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -46,13 +46,27 @@ class RadianceROMConfig extends Config(
new AbstractConfig)
class RadianceConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores() ++
new freechips.rocketchip.subsystem.WithRadianceCores(use_vx_cache = false) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
new AbstractConfig)
class RadianceConfigVortexCache extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(use_vx_cache = true) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
// new freechips.rocketchip.subsystem.WithNoMemPort ++
// new testchipip.WithSbusScratchpad(banks=2) ++
// new testchipip.WithMbusScratchpad(banks=2) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/vcs/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/vcs/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/vcs/op_b.bin") ++
new AbstractConfig
)
class TinyRocketConfig extends Config(
new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
@@ -142,29 +156,6 @@ class MulticlockRocketConfig extends Config(
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new chipyard.config.AbstractConfig)
// DOC include start: MulticlockAXIOverSerialConfig
class MulticlockAXIOverSerialConfig extends Config(
new chipyard.config.WithSystemBusFrequency(250) ++
new chipyard.config.WithPeripheryBusFrequency(250) ++
new chipyard.config.WithMemoryBusFrequency(250) ++
new chipyard.config.WithFrontBusFrequency(50) ++
new chipyard.config.WithTileFrequency(500, Some(1)) ++
new chipyard.config.WithTileFrequency(250, Some(0)) ++
new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(
AsynchronousCrossing().depth,
AsynchronousCrossing().sourceSync) ++
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
new testchipip.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
new chipyard.config.AbstractConfig)
// DOC include end: MulticlockAXIOverSerialConfig
class CustomIOChipTopRocketConfig extends Config(
new chipyard.example.WithCustomChipTop ++
new chipyard.example.WithCustomIOCells ++

4
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -23,7 +23,7 @@ import chipyard.{ExtTLMem}
/**
* Config fragment for adding a BootROM to the SoC
*
*
* @param address the address of the BootROM device
* @param size the size of the BootROM
* @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
@@ -42,7 +42,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt =
// DOC include start: gpio config fragment
/**
* Config fragment for adding a GPIO peripheral device to the SoC
*
*
* @param address the address of the GPIO device
* @param width the number of pins of the GPIO device
*/

23
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
View File

@@ -1,7 +1,7 @@
package chipyard.example
import chisel3._
import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import org.chipsalliance.cde.config.{Field, Parameters}
@@ -41,30 +41,19 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// Serialized TL
val sVal = p(SerialTLKey).get
val serialTLManagerParams = sVal.serialTLManagerParams.get
val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
require(serialTLManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
withClockAndReset(clock, reset) {
val serial_bits = dut.serial_tl_pad.bits
dut.serial_tl_pad.clock := clock
val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
if (DataMirror.directionOf(dut.serial_tl_pad.clock) == Direction.Input) {
dut.serial_tl_pad.clock := clock
}
val harnessRAM = TSIHarness.connectRAM(
lazyDut.system.serdesser.get,
serial_bits,
clock,
reset)
io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset)
io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset)
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
val memSize = serialTLManagerParams.memParams.size
val memBase = serialTLManagerParams.memParams.base
val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits
mem.io.clock := axi_port.clock
mem.io.reset := axi_port.reset
}
}
// JTAG

52
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -128,46 +128,6 @@ class WithSimAXIMem extends OverrideHarnessBinder({
}
})
class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
p(SerialTLKey).map({ sVal =>
val serialTLManagerParams = sVal.serialTLManagerParams.get
val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
require(serialTLManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
ports.map({ port =>
// DOC include start: HarnessClockInstantiatorEx
val memOverSerialTLClock = th.harnessClockInstantiator.requestClockHz("mem_over_serial_tl_clock", memFreq)
val serial_bits = port.bits
port.clock := th.harnessBinderClock
val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
system.serdesser.get,
serial_bits,
memOverSerialTLClock,
th.harnessBinderReset)
// DOC include end: HarnessClockInstantiatorEx
val success = SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), th.harnessBinderClock, th.harnessBinderReset.asBool)
when (success) { th.success := true.B }
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
val memSize = serialTLManagerParams.memParams.size
val memBase = serialTLManagerParams.memParams.base
val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits
mem.io.clock := axi_port.clock
mem.io.reset := axi_port.reset
}
})
})
}
})
class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBinder({
(system: CanHaveMasterAXI4MemPort, th: HasHarnessInstantiators, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
@@ -305,7 +265,9 @@ class WithSimTSIOverSerialTL extends OverrideHarnessBinder({
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val bits = port.bits
port.clock := th.harnessBinderClock
if (DataMirror.directionOf(port.clock) == Direction.Input) {
port.clock := th.harnessBinderClock
}
val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
val success = SimTSI.connect(Some(ram.module.io.tsi), th.harnessBinderClock, th.harnessBinderReset.asBool)
when (success) { th.success := true.B }
@@ -352,12 +314,6 @@ class WithTraceGenSuccess extends OverrideHarnessBinder({
}
})
class WithSimDromajoBridge extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessInstantiators, ports: Seq[TraceOutputTop]) => {
ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
}
})
class WithCospike extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessInstantiators, ports: Seq[TraceOutputTop]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
@@ -391,6 +347,7 @@ class WithClockAndResetFromHarness extends OverrideHarnessBinder({
(system: HasChipyardPRCI, th: HasHarnessInstantiators, ports: Seq[Data]) => {
implicit val p = GetSystemParameters(system)
val clocks = ports.collect { case c: ClockWithFreq => c }
// DOC include start: HarnessClockInstantiatorEx
ports.map ({
case c: ClockWithFreq => {
val clock = th.harnessClockInstantiator.requestClockMHz(s"clock_${c.freqMHz.toInt}MHz", c.freqMHz)
@@ -398,5 +355,6 @@ class WithClockAndResetFromHarness extends OverrideHarnessBinder({
}
case r: AsyncReset => r := th.referenceReset.asAsyncReset
})
// DOC include end: HarnessClockInstantiatorEx
}
})

1
generators/chipyard/src/main/scala/stage/ChipyardOptions.scala
View File

@@ -38,4 +38,3 @@ class ChipyardOptions private[stage] (
if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
}
}

66
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -9,7 +9,7 @@ import chisel3.util.experimental.BoringUtils
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug, ExportDebug, DMI}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{RocketTile}
@@ -108,48 +108,6 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({
}
})
class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = GetSystemParameters(system)
p(SerialTLKey).map({ sVal =>
val serialTLManagerParams = sVal.serialTLManagerParams.get
val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
require(serialTLManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
ports.map({ port =>
val axiClock = th.harnessClockInstantiator.requestClockHz("mem_over_serial_tl_clock", memFreq)
val serial_bits = port.bits
port.clock := th.harnessBinderClock
val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
system.serdesser.get,
serial_bits,
axiClock,
ResetCatchAndSync(axiClock, th.harnessBinderReset.asBool))
TSIBridge(th.harnessBinderClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.harnessBinderReset.asBool)
// connect SimAxiMem
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi4, edge) =>
val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth,
axi4.bits.ar.bits.addr.getWidth,
axi4.bits.ar.bits.id.getWidth)
system match {
case s: BaseSubsystem => FASEDBridge(axi4.clock, axi4.bits, axi4.reset.asBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
}
}
})
})
Nil
}
})
class WithFASEDBridge extends OverrideHarnessBinder({
(system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
@@ -178,12 +136,26 @@ class WithTracerVBridge extends ComposeHarnessBinder({
}
})
class WithDromajoBridge extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) =>
ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil
class WithCospikeBridge extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.tiles
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
nharts = tiles.size,
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
)
ports.map { p => p.traces.zipWithIndex.map(t => CospikeBridge(t._1, t._2, cfg)) }
}
})
class WithTraceGenBridge extends OverrideHarnessBinder({
(system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) =>
ports.map { p => GroundTestBridge(th.harnessBinderClock, p)(system.p) }; Nil

12
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -302,18 +302,6 @@ class FireSimCVA6Config extends Config(
new WithFireSimConfigTweaks ++
new chipyard.CVA6Config)
//**********************************************************************************
//* Multiclock Configurations
//*********************************************************************************/
class FireSimMulticlockAXIOverSerialConfig extends Config(
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++
new testchipip.WithBlockDevice(false) ++ // disable blockdev
new WithDefaultMemModel ++
new WithFireSimDesignTweaks ++ // don't inherit firesim clocking
new chipyard.MulticlockAXIOverSerialConfig
)
//**********************************************************************************
// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations
// - Requires MTModels and MCRams mixins as prefixes to the platform config

2
generators/rocket-chip

Submodule generators/rocket-chip updated: e7e464684e...2166615f21

2
generators/sifive-cache

Submodule generators/sifive-cache updated: 02e002b324...51d400bd32

2
generators/testchipip

Submodule generators/testchipip updated: 3178e5e3ed...d627ad22a3

1
scripts/generate-ckpt.sh
View File

@@ -138,4 +138,3 @@ rm -rf mem.0x80000000.bin
riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF
rm -rf $RAWMEM_ELF

2
scripts/generate-conda-lockfiles.sh
View File

@@ -14,5 +14,5 @@ for TOOLCHAIN_TYPE in riscv-tools esp-tools; do
# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
conda-lock --conda $(which conda) -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE
conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE
done

2
scripts/insert-includes.py
View File

@@ -1,4 +1,4 @@
#!/usr/bin/python
#!/usr/bin/env python
# replaces a `include with the full include file
#

6
scripts/tutorial-patches/build.sbt.patch
View File

@@ -3,7 +3,7 @@ index 302d99e6..0aa0fcb4 100644
--- a/build.sbt
+++ b/build.sbt
@@ -148,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
@@ -14,7 +14,7 @@ index 302d99e6..0aa0fcb4 100644
@@ -220,10 +220,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sha3 = (project in file("generators/sha3"))
- .dependsOn(rocketchip, midasTargetUtils)
- .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -23,6 +23,6 @@ index 302d99e6..0aa0fcb4 100644
+// .dependsOn(rocketchip, midasTargetUtils)
+// .settings(libraryDependencies ++= rocketLibDeps.value)
+// .settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(rocketchip)

2
scripts/uniquify-module-names.py
View File

@@ -201,7 +201,7 @@ def main():
# write model filelist
write_verilog_filelist(uniquified_modules_under_model, verilog_module_filename, args.out_model_filelist)
write_cc_filelist (cc_filelist, args.out_model_filelist)
if __name__=="__main__":
main()

2
sims/firesim

Submodule sims/firesim updated: 67e70ec96d...08b565c8c6

1
sims/verilator/Makefile
View File

@@ -152,6 +152,7 @@ VERILATOR_NONCC_OPTS = \
$(MAX_WIDTH_OPTS) \
$(SIM_PREPROC_DEFINES) \
$(VERILATOR_PREPROC_DEFINES) \
-I$(GEN_COLLATERAL_DIR) \
--top-module $(TB) \
--vpi \
-f $(sim_common_files)

2
sims/xcelium/.gitignore vendored
View File

@@ -1,3 +1,3 @@
*
!.gitignore
*Makefile
*Makefile

1
sims/xcelium/arg-reshuffle
View File

@@ -27,4 +27,3 @@ done
target_args="$target_args +permissive-off"
INPUT_ARGS="$regular_args $target_args"

1
sims/xcelium/xcelium.mk
View File

@@ -62,4 +62,3 @@ PREPROC_DEFINES = \
-define RANDOMIZE_REG_INIT \
-define RANDOMIZE_GARBAGE_ASSIGN \
-define RANDOMIZE_INVALID_ASSIGN

1
software/embench/build.sh
View File

@@ -20,4 +20,3 @@ for bmark in "${bmarks[@]}"
do
cp bd/src/$bmark/$bmark $BUILDDIR/
done

1
tools/dromajo/dromajo-src

Submodule tools/dromajo/dromajo-src deleted from 09fbef4565

59
tools/dromajo/dromajo.mk
View File

@@ -1,59 +0,0 @@
##############################################################
# extra variables/targets ingested by the chipyard make system
##############################################################
DROMAJO_DIR = $(base_dir)/tools/dromajo/dromajo-src/src
DROMAJO_LIB_NAME = dromajo_cosim
DROMAJO_LIB = $(CONDA_PREFIX)/lib/lib$(DROMAJO_LIB_NAME).a
# Dromajo assumes using the default bootrom
DROMAJO_ROM = $(build_dir)/bootrom.rv64.img
DTS_FILE = $(build_dir)/$(long_name).dts
DROMAJO_DTB = $(build_dir)/$(long_name).dtb
$(DTS_FILE): $(FIRRTL_FILE)
$(DROMAJO_DTB): $(DTS_FILE)
dtc -I dts -O dtb -o $(DROMAJO_DTB) $(DTS_FILE)
DROMAJO_SRCS = $(call lookup_srcs,$(DROMAJO_DIR),cc) $(call lookup_srcs,$(DROMAJO_DIR),h)
$(DROMAJO_LIB): $(DROMAJO_SRCS)
$(MAKE) -C $(DROMAJO_DIR)
# depending on where the simulation is done, use the auto-variable or the hardcoded defined one
ifeq ($(BINARY),)
DROMAJO_BIN = $(<)
else
DROMAJO_BIN = $(BINARY)
endif
DROMAJO_FLAGS = +drj_dtb=$(DROMAJO_DTB) +drj_rom=$(DROMAJO_ROM) +drj_bin=$(DROMAJO_BIN)
DROMAJO_PARAMS_FILE = $(build_dir)/$(long_name).dromajo_params.h
DROMAJO_PARAMS_SYMLINK = $(build_dir)/dromajo_params.h
$(DROMAJO_PARAMS_FILE): $(FIRRTL_FILE)
$(DROMAJO_PARAMS_SYMLINK): $(DROMAJO_PARAMS_FILE)
rm -rf $(DROMAJO_PARAMS_SYMLINK)
ln -s $(DROMAJO_PARAMS_FILE) $(DROMAJO_PARAMS_SYMLINK)
##################################################################
# THE FOLLOWING MUST BE += operators
##################################################################
# simargs needed (i.e. like +drj_test=hello)
ifdef ENABLE_DROMAJO
EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS)
# CC flags needed for all simulations
EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR)
# sourced needed for simulation
EXTRA_SIM_SOURCES += $(DROMAJO_LIB)
# requirements needed for simulation
EXTRA_SIM_REQS += $(DROMAJO_PARAMS_SYMLINK) $(DROMAJO_LIB) $(DROMAJO_DTB)
endif

2
variables.mk
View File

@@ -139,7 +139,7 @@ ifeq ($(SUB_PROJECT),constellation)
TOP ?= NoC
endif
# For graphics developers
ifeq ($(SUB_PROJECT),graphics)
ifeq ($(SUB_PROJECT),coalescer)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)

2
vlsi/example-designs/sky130-commercial.yml
View File

@@ -9,7 +9,7 @@ vlsi.inputs.clocks: [
# If overriding the placement constraints in example-sky130.yml,
# ensure one of the toplevel margin sides corresponding with the power pin metal layers
# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
# For example, in example-sky130.yml we set
# For example, in example-sky130.yml we set
# par.generate_power_straps_options.by_tracks.pin_layers: 'met5' # horizontal layer
# therefore we must also set:
# vlsi.inputs.placement_constraints:

2
vlsi/example-designs/sky130-openroad-rockettile.yml
View File

@@ -44,7 +44,7 @@ vlsi.inputs.placement_constraints:
x: 50
y: 1250
orientation: r90
# tag array
- path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro

4
vlsi/example-designs/sky130-openroad.yml
View File

@@ -28,7 +28,7 @@ par.openroad:
clock_tree_resize.setup_margin: 0.0
clock_tree_resize.hold_margin: 0.20
global_route_resize.hold_margin: 0.60
clock_tree_resize.hold_max_buffer_percent: 80
clock_tree_resize.hold_max_buffer_percent: 80
global_placement.routing_adjustment: 0.5
global_route.routing_adjustment: 0.3
@@ -76,7 +76,7 @@ vlsi.inputs.placement_constraints:
x: 50
y: 1250
orientation: r90
# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro

11
vlsi/example-openroad.yml
View File

@@ -1,10 +1,11 @@
# Tool options. Replace with your tool plugin of choice.
vlsi.core.build_system: make
# Yosys
# Synthesis: Yosys
vlsi.core.synthesis_tool: "hammer.synthesis.yosys"
# OpenROAD
# Place-and-Route: OpenROAD
vlsi.core.par_tool: "hammer.par.openroad"
# Magic
vlsi.core.drc_tool: "hammer.drc.magic"
# Netgen
# DRC: KLayout or Magic (comment other one out)
vlsi.core.drc_tool: "hammer.drc.klayout"
# vlsi.core.drc_tool: "hammer.drc.magic"
# LVS: Netgen
vlsi.core.lvs_tool: "hammer.lvs.netgen"