Merge pull request #195 from ucb-bar/doc-update

Quick Doc Fixes

docs/Chipyard-Basics/Building-A-Chip.rst

@@ -2,4 +2,5 @@
 
 Building A Chip
 ==============================
+
 TODO

docs/Customization/index.rst

@@ -12,6 +12,7 @@ Hit next to get started!
 .. toctree::
    :maxdepth: 2
    :caption: Customization:
+
    Heterogeneous-SoCs
    Adding-An-Accelerator
    Memory-Hierarchy

docs/Quick-Start.rst

@@ -21,7 +21,7 @@ We need to install the RISC-V toolchain in order to be able to run RISC-V progra
 This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``.
 To build the toolchains, you should run:
 
-::
+.. code-block:: shell
 
     ./scripts/build-toolchains.sh
 

docs/Simulation/FPGA-Accelerated-Simulators.rst

@@ -56,6 +56,7 @@ classes from other generator projects into FireChip. For example, assuming you C
 config looks as following:
 
 .. code-block:: scala
+
   class CustomConfig extends Config(
     new WithInclusiveCache ++
     new myproject.MyCustomConfig ++
@@ -66,6 +67,7 @@ Then the equivalent FireChip config (in `generators/firechip/src/main/scala/Targ
 will look as follows:
 
 .. code-block:: scala
+
   class FireSimCustomConfig extends Config(
     new WithBootROM ++
     new WithPeripheryBusFrequency(BigInt(3200000000L)) ++

docs/index.rst

@@ -10,10 +10,8 @@ Chipyard is a a framework for designing and evaluating full-system hardware usin
 It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip.
 New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info.
 
-
 .. include:: Quick-Start.rst
 
-
 .. toctree::
    :maxdepth: 3
    :caption: Contents: