Run pre-commit on all files

docs/Generators/Gemmini.rst

@@ -7,4 +7,3 @@ Gemmini enables architects to make useful insights into how different components
 Check out `Gemmini's documentation <https://github.com/ucb-bar/gemmini/blob/master/README.md>`__ to learn how to generate, simulate, and profile DNN accelerators with Gemmini and Chipyard.
 
 .. image:: ../_static/images/gemmini-system.png
-

docs/Generators/Ibex.rst

@@ -11,4 +11,4 @@ The core exposes a custom memory interface, interrupt ports, and other misc. por
 
 While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
 
-For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.
+For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.

docs/Generators/SHA3.rst

@@ -79,5 +79,3 @@ this config fragment is shown here:
 
 The SHA3 example baremetal and Linux tests are located in the SHA3 repository.
 Please refer to its `README.md <https://github.com/ucb-bar/sha3/blob/master/README.md>`_ for more information on how to run/build the tests.
-
-

docs/Generators/Sodor.rst

@@ -4,7 +4,7 @@ Sodor Core
 `Sodor <https://github.com/ucb-bar/riscv-sodor>`__ is a collection of 5 simple RV32MI cores designed for educational purpose.
 The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`.
 The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT**
-support external memory. 
+support external memory.
 
 The five available cores and their corresponding generator configuration are:
 

docs/Generators/TestChipIP.rst

@@ -69,7 +69,7 @@ to the TLXbar provided by RocketChip, but uses ring networks internally rather
 than crossbars. This can be useful for chips with very wide TileLink networks
 (many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve
 wire routing congestion. Documentation on how to use the ring network can be
-found in :ref:`Customization/Memory-Hierarchy:The System Bus`. The implementation itself can be found 
+found in :ref:`Customization/Memory-Hierarchy:The System Bus`. The implementation itself can be found
 `here <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Ring.scala>`_,
 and may serve as an example of how to implement your own TileLink network with
 a different topology.

docs/Generators/index.rst

@@ -34,4 +34,3 @@ so changes to the generators themselves will automatically be used when building
    NVDLA
    Sodor
    Mempress
-