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2022-12-21 15:59:46 -08:00
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1
LICENSE
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@@ -27,4 +27,3 @@ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

2
docs/Advanced-Concepts/CDEs.rst
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@@ -107,5 +107,3 @@ In this example, note how ``up(SomeKeyY, site)`` in ``WithXEqualsYUp`` will refe
Also note that again, ``site`` must be recursively passed through the call to ``up``.

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docs/Advanced-Concepts/Debugging-RTL.rst
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@@ -96,11 +96,10 @@ To run overnight tests (repeated random tests), run
make CONFIG=CustomConfig TORTURE_ONIGHT_OPTIONS=<overnight options> torture-overnight
You can find the overnight options in `overnight/src/main/scala/main.scala` in the torture repo.
You can find the overnight options in `overnight/src/main/scala/main.scala` in the torture repo.
Firesim Debugging
---------------------------
Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim
FPGA-accelerated simulation. See the FireSim
`documentation <https://docs.fires.im/en/latest/>`__ for more detail.

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docs/Advanced-Concepts/index.rst
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@@ -16,4 +16,3 @@ They expect you to know about Chisel, Parameters, configs, etc.
CDEs
Harness-Clocks
Managing-Published-Scala-Dependencies

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docs/Chipyard-Basics/index.rst
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@@ -19,5 +19,3 @@ Hit next to get started!
Development-Ecosystem
Configs-Parameters-Mixins
Initial-Repo-Setup

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docs/Customization/DMA-Devices.rst
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@@ -35,5 +35,3 @@ Once we've created our top-level module including the DMA widget, we can create
:language: scala
:start-after: DOC include start: InitZeroRocketConfig
:end-before: DOC include end: InitZeroRocketConfig

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docs/Customization/Keys-Traits-Configs.rst
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@@ -75,5 +75,3 @@ We can use this config fragment when composing our configs.
.. note::
Readers who want more information on the configuration system may be interested in reading :ref:`cdes`.

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docs/Customization/MMIO-Peripherals.rst
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@@ -138,5 +138,3 @@ Now with all of that done, we can go ahead and run our simulation.
cd sims/verilator
make CONFIG=GCDTLRocketConfig BINARY=../../tests/gcd.riscv run-binary

1
docs/Customization/RoCC-Accelerators.rst
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@@ -67,4 +67,3 @@ For instance, if we wanted to add the previously defined accelerator and route c
new RocketConfig)
To add RoCC instructions in your program, use the RoCC C macros provided in ``tests/rocc.h``. You can find examples in the files ``tests/accum.c`` and ``charcount.c``.

1
docs/Generators/Gemmini.rst
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@@ -7,4 +7,3 @@ Gemmini enables architects to make useful insights into how different components
Check out `Gemmini's documentation <https://github.com/ucb-bar/gemmini/blob/master/README.md>`__ to learn how to generate, simulate, and profile DNN accelerators with Gemmini and Chipyard.
.. image:: ../_static/images/gemmini-system.png

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docs/Generators/Ibex.rst
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@@ -11,4 +11,4 @@ The core exposes a custom memory interface, interrupt ports, and other misc. por
While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.
For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.

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docs/Generators/SHA3.rst
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@@ -79,5 +79,3 @@ this config fragment is shown here:
The SHA3 example baremetal and Linux tests are located in the SHA3 repository.
Please refer to its `README.md <https://github.com/ucb-bar/sha3/blob/master/README.md>`_ for more information on how to run/build the tests.

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docs/Generators/Sodor.rst
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@@ -4,7 +4,7 @@ Sodor Core
`Sodor <https://github.com/ucb-bar/riscv-sodor>`__ is a collection of 5 simple RV32MI cores designed for educational purpose.
The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`.
The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT**
support external memory.
support external memory.
The five available cores and their corresponding generator configuration are:

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docs/Generators/TestChipIP.rst
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@@ -69,7 +69,7 @@ to the TLXbar provided by RocketChip, but uses ring networks internally rather
than crossbars. This can be useful for chips with very wide TileLink networks
(many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve
wire routing congestion. Documentation on how to use the ring network can be
found in :ref:`Customization/Memory-Hierarchy:The System Bus`. The implementation itself can be found
found in :ref:`Customization/Memory-Hierarchy:The System Bus`. The implementation itself can be found
`here <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Ring.scala>`_,
and may serve as an example of how to implement your own TileLink network with
a different topology.

1
docs/Generators/index.rst
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@@ -34,4 +34,3 @@ so changes to the generators themselves will automatically be used when building
NVDLA
Sodor
Mempress

4
docs/Prototyping/VCU118.rst
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@@ -122,7 +122,7 @@ Additionally, these instructions assume you are using Linux with ``sudo`` privil
3. The VCU118 bootrom assumes that the Linux binary to load into memory will be located on sector 34 of the SDCard.
Change the default partition alignment to `1` so you can write to sector `34`.
Do this with the `l` command from the expert menu (opened with 'x', closed with 'm').
Do this with the `l` command from the expert menu (opened with 'x', closed with 'm').
4. Create a 512MiB partition to store the Linux binary (this can be smaller but it must be larger than the size of the Linux binary).
Use `n`, partion number 1 and select sector 34, with size `+1048576` (corresponding to 512MiB).
@@ -162,4 +162,4 @@ To interact with Linux via the UART console, you can connect to the serial port
screen -S FPGA_UART_CONSOLE /dev/ttyUSB1 115200
Once connected, you should see the binary being loaded as well as Linux output (in some cases you might need to reset the DUT). Sign in as 'root' with password 'fpga'.
Once connected, you should see the binary being loaded as well as Linux output (in some cases you might need to reset the DUT). Sign in as 'root' with password 'fpga'.

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docs/TileLink-Diplomacy-Reference/Diplomacy-Connectors.rst
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@@ -9,7 +9,7 @@ library provides four operators that can be used to form edges between nodes.
This is the basic connection operator. It is the same syntax as the Chisel
uni-directional connector, but it is not equivalent. This operator connects
Diplomacy nodes, not Chisel bundles.
Diplomacy nodes, not Chisel bundles.
The basic connection operator always creates a single edge between the two
nodes.

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docs/TileLink-Diplomacy-Reference/Register-Router.rst
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@@ -2,15 +2,15 @@ Register Router
===============
Memory-mapped devices generally follow a common pattern. They expose a set
of registers to the CPUs. By writing to a register, the CPU can change the
of registers to the CPUs. By writing to a register, the CPU can change the
device's settings or send a command. By reading from a register, the CPU can
query the device's state or retrieve results.
While designers can manually instantiate a manager node and write the logic
While designers can manually instantiate a manager node and write the logic
for exposing registers themselves, it's much easier to use RocketChip's
``regmap`` interface, which can generate most of the glue logic.
For TileLink devices, you can use the ``regmap`` interface by extending
For TileLink devices, you can use the ``regmap`` interface by extending
the ``TLRegisterRouter`` class, as shown in :ref:`mmio-accelerators`,
or you can create a regular LazyModule and instantiate a ``TLRegisterNode``.
This section will focus on the second method.

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docs/TileLink-Diplomacy-Reference/Widgets.rst
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@@ -465,6 +465,3 @@ if you want multi-beat reads/writes.
AXI4RAM only supports AXI4-Lite operations, so multi-beat reads/writes and
reads/writes smaller than full-width are not supported. Use an ``AXI4Fragmenter``
if you want to use the full AXI4 protocol.

8
docs/VLSI/ASAP7-Tutorial.rst
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@@ -54,8 +54,8 @@ Prerequisites
* Genus, Innovus, Voltus, VCS, and Calibre licenses
* For ASAP7 specifically (`README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ for more details):
* First, download the `ASAP7 v1p7 PDK <https://github.com/The-OpenROAD-Project/asap7>`__ (we recommend shallow-cloning or downloading an archive of the repository). Then, download the `encrypted Calibre decks tarball <http://asap.asu.edu/asap/>`__ tarball to a directory of choice (e.g. the root directory of the PDK) but do not extract it like the instructions say. The tech plugin is configured to extract the tarball into a cache directory for you.
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision.
* First, download the `ASAP7 v1p7 PDK <https://github.com/The-OpenROAD-Project/asap7>`__ (we recommend shallow-cloning or downloading an archive of the repository). Then, download the `encrypted Calibre decks tarball <http://asap.asu.edu/asap/>`__ tarball to a directory of choice (e.g. the root directory of the PDK) but do not extract it like the instructions say. The tech plugin is configured to extract the tarball into a cache directory for you.
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision.
Initial Setup
-------------
@@ -64,7 +64,7 @@ In the Chipyard root, run:
.. code-block:: shell
./scripts/init-vlsi.sh asap7
to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
@@ -116,7 +116,7 @@ Place-and-Route
After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.

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docs/VLSI/Building-A-Chip.rst
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@@ -50,5 +50,3 @@ Running the VLSI tool flow
For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`.

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docs/VLSI/Hammer.rst
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@@ -29,10 +29,10 @@ Hooks are modifications to steps or actions that are programmatically defined in
VLSI Flow Control
-----------------
Sometimes we want more fine-grained control of the VLSI flow than at the action level.
The Hammer flow supports being able to start/stop before/after any of the steps in a particular action.
The Hammer flow supports being able to start/stop before/after any of the steps in a particular action.
See the `Hammer documentation on Flow Control <https://docs.hammer-eda.org/en/latest/Hammer-Use/Flow-Control.html>`__ for a full list and description of the options.
The ``Makefile`` in the ``vlsi`` directory passes this extra information via the ``HAMMER_EXTRA_ARGS`` variable.
This variable can also be used to specify additional YAML configurations that may have
This variable can also be used to specify additional YAML configurations that may have
changed or been omitted from the inital build.

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docs/VLSI/Sky130-Commercial-Tutorial.rst
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@@ -57,7 +57,7 @@ In the Chipyard root, run:
.. code-block:: shell
./scripts/init-vlsi.sh sky130
to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
@@ -76,14 +76,14 @@ To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build
make buildfile tutorial=sky130-commercial
The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
It needs to be re-run if environment variables are changed.
The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
It needs to be re-run if environment variables are changed.
It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-commercial``,
which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described below
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
@@ -102,13 +102,13 @@ example-sky130.yml
^^^^^^^^^^^^^^^^^^
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
for details about the PDK setup.
example-tools.yml
^^^^^^^^^^^^^^^^^
This contains the Hammer configuration for a commercial tool flow.
This contains the Hammer configuration for a commercial tool flow.
It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre).
Synthesis
@@ -127,7 +127,7 @@ Place-and-Route
After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
@@ -142,9 +142,9 @@ To run DRC & LVS, and view the results in Calibre:
make lvs tutorial=sky130-commercial
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
For this reason, the ``example-vlsi-sky130`` script black-boxes the SRAMs for DRC/LVS analysis.
For this reason, the ``example-vlsi-sky130`` script black-boxes the SRAMs for DRC/LVS analysis.
Simulation
^^^^^^^^^^

24
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
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@@ -48,7 +48,7 @@ Prerequisites
* Yosys (synthesis), install `from source <https://yosyshq.net/yosys/download.html>`__ or `using conda <https://anaconda.org/TimVideos/yosys>`__
* OpenROAD (place-and-route), install `from source <https://openroad.readthedocs.io/en/latest/main/README.html#install-dependencies>`__
* Magic (DRC), install `from source <http://www.opencircuitdesign.com/magic/install.html>`__
* NetGen (LVS), install `from source <http://www.opencircuitdesign.com/netgen/install.html>`__ or `using conda <https://anaconda.org/conda-forge/netgen>`__
* NetGen (LVS), install `from source <http://www.opencircuitdesign.com/netgen/install.html>`__ or `using conda <https://anaconda.org/conda-forge/netgen>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
@@ -59,8 +59,8 @@ In the Chipyard root, run:
.. code-block:: shell
./scripts/init-vlsi.sh sky130 openroad
to pull the Hammer submodule. Note that for technologies other than ``sky130`` or ``asap7``, the tech plugin submodule is cloned into the ``vlsi`` folder,
to pull the Hammer submodule. Note that for technologies other than ``sky130`` or ``asap7``, the tech plugin submodule is cloned into the ``vlsi`` folder,
and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
Pull the Hammer environment into the shell:
@@ -79,14 +79,14 @@ To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build
make buildfile tutorial=sky130-openroad
The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
It needs to be re-run if environment variables are changed.
The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
It needs to be re-run if environment variables are changed.
It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``,
which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
@@ -105,14 +105,14 @@ example-sky130.yml
^^^^^^^^^^^^^^^^^^
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.sky130.<sky130A, openram_lib>`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
First, set ``technology.sky130.<sky130A, openram_lib>`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
for details about the PDK setup.
example-openroad.yml
^^^^^^^^^^^^^^^^^^^^
This contains the Hammer configuration for the OpenROAD tool flow.
This contains the Hammer configuration for the OpenROAD tool flow.
It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen).
Synthesis
@@ -122,7 +122,7 @@ Synthesis
make syn tutorial=sky130-openroad
Post-synthesis logs and collateral are in ``build/syn-rundir``.
Post-synthesis logs and collateral are in ``build/syn-rundir``.
.. The raw quality of results data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a work in progress.
@@ -162,7 +162,7 @@ To run DRC & LVS:
make drc tutorial=sky130-openroad
make lvs tutorial=sky130-openroad
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
@@ -172,7 +172,7 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
.. code-block:: shell
# the following two statements are equivalent because the
# the following two statements are equivalent because the
# extraction step immediately precedes the write_design step
make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"
@@ -187,4 +187,4 @@ Documentation
For more information about Hammer's underlying implementation, visit the `Hammer documentation website <https://docs.hammer-eda.org/en/latest/index.html>`__.
For details about the plugins used in this tutorial, check out the `OpenROAD tool plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/par/openroad>`__
and `Sky130 tech plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/sky130>`__.
and `Sky130 tech plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/sky130>`__.

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fpga/src/main/scala/arty/TestHarness.scala
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@@ -38,4 +38,3 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
}

2
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -91,7 +91,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
}
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
val vc707Outer = _outer
val reset = IO(Input(Bool()))

1
fpga/src/main/scala/vcu118/CustomOverlays.scala
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@@ -107,4 +107,3 @@ class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShe
extends DDRShellPlacer[VCU118FPGATestHarness] {
def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
}

6
generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v
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@@ -17,7 +17,7 @@ module GCDMMIOBlackBox
localparam S_IDLE = 2'b00, S_RUN = 2'b01, S_DONE = 2'b10;
reg [1:0] state;
reg [1:0] state;
reg [WIDTH-1:0] tmp;
assign input_ready = state == S_IDLE;
@@ -34,12 +34,12 @@ module GCDMMIOBlackBox
else if (state == S_DONE && output_ready)
state <= S_IDLE;
end
always @(posedge clock) begin
if (state == S_IDLE && input_valid) begin
gcd <= x;
tmp <= y;
end else if (state == S_RUN) begin
end else if (state == S_RUN) begin
if (gcd > tmp)
gcd <= gcd - tmp;
else

1
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -33,4 +33,3 @@ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
// anyways, they probably need to be explicitly clocked.
lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) { }
}

1
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -83,4 +83,3 @@ class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends Bas
// This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts(InSubsystem)
}

1
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -108,4 +108,3 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
implicitHarnessClockBundle.reset := reset
p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle)
}

1
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -86,4 +86,3 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
:= tileResetSetter
:= allClockGroupsNode)
}

4
generators/chipyard/src/main/scala/clocking/TileClockGater.scala
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@@ -14,9 +14,9 @@ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
/** This node adds clock gating control registers.
/** This node adds clock gating control registers.
* If deploying on a platform which does not support clock gating, deasserting the enable
* flag will generate the registers, preserving the same memory map and behavior, but will not
* flag will generate the registers, preserving the same memory map and behavior, but will not
* generate any gaters
*/
class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule

2
generators/chipyard/src/main/scala/config/IbexConfigs.scala
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@@ -12,4 +12,4 @@ import freechips.rocketchip.config.{Config}
class IbexConfig extends Config(
new ibex.WithNIbexCores(1) ++
new chipyard.config.AbstractConfig)
new chipyard.config.AbstractConfig)

1
generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
View File

@@ -20,4 +20,3 @@ class Sha3RocketPrintfConfig extends Config(
new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

1
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -75,4 +75,3 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
})

1
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -68,4 +68,3 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
))
}
})

1
generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
View File

@@ -11,4 +11,3 @@ class TraceGenTop(implicit p: Parameters) extends TraceGenSystem
class WithTracegenSystem extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => new TraceGenTop()(p)
})

1
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
View File

@@ -145,4 +145,3 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
class WithStreamingPassthrough extends Config((site, here, up) => {
case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
})

1
generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala
View File

@@ -23,4 +23,3 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
)
)
}

2
generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala
View File

@@ -14,7 +14,7 @@ class SimplePllConfigurationSpec extends org.scalatest.flatspec.AnyFlatSpec {
def trySuccessfulConf(requestedFreqs: Seq[Double], expected: Double): Unit = {
val freqStr = requestedFreqs.mkString(", ")
it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in {
it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in {
val conf = genConf(requestedFreqs)
conf.emitSummaries
assert(expected == conf.referenceFreqMHz)

2
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -109,7 +109,7 @@ class WithFireSimHighPerfClocking extends Config(
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
class WithFireSimConfigTweaks extends Config(
// 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
// Using some other frequency will require runnings the FASED runtime configuration generator
// Using some other frequency will require runnings the FASED runtime configuration generator
// to generate faithful DDR3 timing values.
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz)

1
scripts/fix-open-files.sh
View File

@@ -11,4 +11,3 @@ fi
# in any case, set the soft limit to the same value as the hard limit
ulimit -Sn $(ulimit -Hn)

6
scripts/tutorial-patches/build.sbt.patch
View File

@@ -3,7 +3,7 @@ index ec36a85f..c0c2849a 100644
--- a/build.sbt
+++ b/build.sbt
@@ -146,7 +146,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
@@ -14,7 +14,7 @@ index ec36a85f..c0c2849a 100644
@@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sha3 = (project in file("generators/sha3"))
- .dependsOn(rocketchip, midasTargetUtils)
- .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -25,6 +25,6 @@ index ec36a85f..c0c2849a 100644
+// .settings(libraryDependencies ++= rocketLibDeps.value)
+// .settings(chiselTestSettings)
+// .settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(testchipip, rocketchip)

2
tests/blkdev.h
View File

@@ -24,7 +24,7 @@ static inline size_t blkdev_max_req_len(void)
static inline unsigned int blkdev_send_request(
unsigned long addr,
unsigned int offset,
unsigned int offset,
unsigned int len,
unsigned char write)
{

1
tests/spiflash.py
View File

@@ -8,4 +8,3 @@ with open(outfile, 'wb') as f:
for i in range(0,0x100000,4):
check = 0xdeadbeef - i
f.write(check.to_bytes(4,'little'))

2
tests/streaming-fir.c
View File

@@ -60,6 +60,6 @@ int main(void)
} else {
printf("\n\nAll tests passed\n\n");
}
return 0;
}

2
tests/streaming-passthrough.c
View File

@@ -44,6 +44,6 @@ int main(void)
} else {
printf("\n\nAll tests passed\n\n");
}
return 0;
}

4
vlsi/example-asap7.yml
View File

@@ -20,7 +20,7 @@ vlsi.inputs.clocks: [
{name: "clock_clock", period: "1ns", uncertainty: "0.1ns"}
]
# Generate Make include to aid in flow
# Generate Make include to aid in flow
vlsi.core.build_system: make
# Placement Constraints
@@ -52,7 +52,7 @@ vlsi.inputs.placement_constraints:
top_layer: "M4"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
type: hardmacro
x: 675
x: 675
y: 25
orientation: "r0"
top_layer: "M4"

2
vlsi/example-design.yml
View File

@@ -1,6 +1,6 @@
# General Hammer Inputs Related to the Design and Build System
# Generate Make include to aid in flow
# Generate Make include to aid in flow
vlsi.core.build_system: make
vlsi.core.max_threads: 12

13
vlsi/example-designs/sky130-commercial.yml
View File

@@ -19,7 +19,6 @@ par.generate_power_straps_options:
- met5
blockage_spacing_met2: 4.0
blockage_spacing_met4: 2.0
blockage_spacing_met4: 2.0
track_width: 3
track_width_met5: 1
track_spacing: 5
@@ -74,22 +73,22 @@ vlsi.inputs.placement_constraints:
y: 1900
orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
type: hardmacro
x: 1000
x: 1000
y: 1300
orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
type: hardmacro
x: 1000
x: 1000
y: 700
orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
type: hardmacro
x: 1000
x: 1000
y: 100
orientation: r0
@@ -124,7 +123,7 @@ vlsi.inputs.placement_constraints:
x: 2000
y: 1900
orientation: "r0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
type: hardmacro
x: 2750

12
vlsi/example-designs/sky130-openroad.yml
View File

@@ -51,22 +51,22 @@ vlsi.inputs.placement_constraints:
y: 1900
orientation: r0
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
type: hardmacro
x: 1000
x: 1000
y: 1300
orientation: r0
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
type: hardmacro
x: 1000
x: 1000
y: 700
orientation: r0
- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
type: hardmacro
x: 1000
x: 1000
y: 100
orientation: r0
@@ -87,4 +87,4 @@ vlsi.inputs.placement_constraints:
type: hardmacro
x: 3450
y: 1300
orientation: r0
orientation: r0

2
vlsi/example-designs/sky130-rocket.yml
View File

@@ -19,4 +19,4 @@ vlsi.inputs.placement_constraints:
left: 10
right: 10
top: 10
bottom: 10
bottom: 10

5
vlsi/example-sky130.yml
View File

@@ -7,7 +7,7 @@ vlsi.core.max_threads: 12
# Technology paths
technology.sky130:
sky130A: "/path/to/sky130A"
openram_lib: "/path/to/sky130_sram_macros"
openram_lib: "/path/to/sky130_sram_macros"
# this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
sky130_nda: "/path/to/skywater-src-nda"
@@ -23,7 +23,7 @@ vlsi.inputs.clocks: [
{name: "clock_clock", period: "10ns", uncertainty: "1ns"}
]
# Generate Make include to aid in flow
# Generate Make include to aid in flow
vlsi.core.build_system: make
# Placement Constraints
@@ -54,7 +54,6 @@ par.generate_power_straps_options:
- met5
blockage_spacing_met2: 4.0
blockage_spacing_met4: 2.0
blockage_spacing_met4: 2.0
track_width: 3
track_width_met5: 1
track_spacing: 5

2
vlsi/example-vlsi
View File

@@ -56,7 +56,7 @@ class ExampleDriver(CLIDriver):
# The target step in any of the above calls may be a default step or another one of your custom hooks
]
return extra_hooks
return extra_hooks
if __name__ == '__main__':
ExampleDriver().main()

2
vlsi/example-vlsi-sky130
View File

@@ -58,7 +58,7 @@ class ExampleDriver(CLIDriver):
# The target step in any of the above calls may be a default step or another one of your custom hooks
]
return extra_hooks
return extra_hooks
if __name__ == '__main__':
ExampleDriver().main()

4
vlsi/tutorial.mk
View File

@@ -20,7 +20,7 @@ ifeq ($(tutorial),sky130-commercial)
TECH_CONF ?= example-sky130.yml
DESIGN_CONF ?= example-designs/sky130-commercial.yml
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
VLSI_OBJ_DIR ?= build-sky130-commercial
endif
@@ -31,6 +31,6 @@ ifeq ($(tutorial),sky130-openroad)
TECH_CONF ?= example-sky130.yml
DESIGN_CONF ?= example-designs/sky130-openroad.yml
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
VLSI_OBJ_DIR ?= build-sky130-openroad
endif