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abejgonzalez
2022-12-21 15:59:46 -08:00
parent d63c3cb72e
commit 292cc753ce
59 changed files with 76 additions and 115 deletions
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13
vlsi/example-designs/sky130-commercial.yml
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@@ -19,7 +19,6 @@ par.generate_power_straps_options:
- met5
blockage_spacing_met2: 4.0
blockage_spacing_met4: 2.0
blockage_spacing_met4: 2.0
track_width: 3
track_width_met5: 1
track_spacing: 5
@@ -74,22 +73,22 @@ vlsi.inputs.placement_constraints:
y: 1900
orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
type: hardmacro
x: 1000
x: 1000
y: 1300
orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
type: hardmacro
x: 1000
x: 1000
y: 700
orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
type: hardmacro
x: 1000
x: 1000
y: 100
orientation: r0
@@ -124,7 +123,7 @@ vlsi.inputs.placement_constraints:
x: 2000
y: 1900
orientation: "r0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
type: hardmacro
x: 2750