Merge remote-tracking branch 'origin/main' into tcdtm

.github/scripts/defaults.sh

@@ -53,7 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
-mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig verilog"
+mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -36,10 +36,10 @@ class ChipLikeQuadRocketConfig extends Config(
   new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++
 
   // Set up the crossings
+  new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++  // Add Async crossing between SBUS and FBUS
   new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++  // Add Async crossing between PBUS and CBUS
   new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++  // Add Async crossings between backside of L2 and MBUS
   new testchipip.WithAsynchronousSerialSlaveCrossing ++                      // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
-  new testchipip.WithSerialTLAsyncResetQueue ++                              // Add Async reset queue to block ready while in reset
 
   new chipyard.config.AbstractConfig)
 

tests/Makefile

@@ -1,7 +1,29 @@
-GCC=riscv64-unknown-elf-gcc
-OBJDUMP=riscv64-unknown-elf-objdump
-CFLAGS= -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall
-LDFLAGS= -static
+#################################
+# RISCV Toolchain
+#################################
+
+PREFIX = riscv64-unknown-elf-
+
+GCC = $(PREFIX)gcc
+CXX = $(PREFIX)g++
+CP = $(PREFIX)objcopy
+OBJDUMP = $(PREFIX)objdump
+DG = $(PREFIX)gdb
+SIZE = $(PREFIX)size
+
+
+#################################
+# Flags
+#################################
+
+# SoC Settings
+ARCH = rv64imafdc
+ABI = lp64d
+ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI)
+
+CFLAGS  = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall
+CFLAGS += $(ARCHFLAGS)
+LDFLAGS = -static
 
 include libgloss.mk
 
@@ -9,16 +31,16 @@ PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
            streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \
            hello
 
-spiflash.img: spiflash.py
-	python3 $<
 
 .DEFAULT_GOAL := default
 
-.PHONY: default
-default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img
 
-.PHONY: dumps
-dumps: $(addsuffix .dump,$(PROGRAMS))
+#################################
+# Build
+#################################
+
+spiflash.img: spiflash.py
+	python3 $<
 
 %.o: %.S
 	$(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@
@@ -33,7 +55,17 @@ dumps: $(addsuffix .dump,$(PROGRAMS))
 	$(OBJDUMP) -D $< > $@
 
 
+#################################
+# Recipes
+#################################
+
 .PHONY: clean
 clean:
 	rm -f *.riscv *.o *.dump
 	$(if $(libgloss),rm -rf $(libgloss_builddir)/)
+
+.PHONY: default
+default: $(addsuffix .riscv, $(PROGRAMS)) spiflash.img
+
+.PHONY: dumps
+dumps: $(addsuffix .dump, $(PROGRAMS))