Cleanup config + fragments | Remove reference clk div/rst catch in harness [ci skip]

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -205,8 +205,13 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
   )}
 })
 
-class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz)
-class WithSpecificTileFrequency(hartId: Int, fMHz: Double) extends chipyard.ClockNameContainsAssignment(s"tile_$hartId", fMHz)
+class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({
+    hartId match {
+      case Some(id) => s"tile_$id"
+      case None => "tile"
+    }
+  },
+  fMHz)
 
 class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
   case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -83,9 +83,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({
 // DOC include start: WithUARTAdapter
 class WithUARTAdapter extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
-    withClockAndReset(th.harnessClock, th.harnessReset) {
-      UARTAdapter.connect(ports)(system.p)
-    }
+    UARTAdapter.connect(ports)(system.p)
   }
 })
 // DOC include end: WithUARTAdapter

generators/chipyard/src/main/scala/TestHarness.scala

@@ -57,13 +57,19 @@ class HarnessClockInstantiator {
       divider.io.clk_out
     }
 
-    // TODO: on the implicit clock just create a passthrough (don't instantiate a divider + reset catch)
     // connect wires to clock source
     for (sinkParams <- sinks) {
-      val div = pllConfig.sinkDividerMap(sinkParams)
-      val divClock = dividedClocks.getOrElse(div, instantiateDivider(div))
+      // bypass the reference freq. (don't create a divider + reset sync)
+      val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) {
+        val div = pllConfig.sinkDividerMap(sinkParams)
+        val divClock = dividedClocks.getOrElse(div, instantiateDivider(div))
+        (divClock, ResetCatchAndSync(divClock, refClock.reset.asBool))
+      } else {
+        (refClock.clock, refClock.reset)
+      }
+
       _clockMap(sinkParams.name.get)._2.clock := divClock
-      _clockMap(sinkParams.name.get)._2.reset := ResetCatchAndSync(divClock, refClock.reset.asBool)
+      _clockMap(sinkParams.name.get)._2.reset := divReset
     }
   }
 }

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -1,8 +1,7 @@
 package chipyard
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing, RationalCrossing}
-import freechips.rocketchip.util.{SlowToFast}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
 // Rocket Configs
@@ -215,20 +214,22 @@ class LBWIFRocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class MulticlockAXIOverSerialConfig extends Config(
-  new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
-
   new chipyard.config.WithSystemBusFrequencyAsDefault ++
-  new chipyard.config.WithSystemBusFrequency(4000) ++
-  new chipyard.config.WithPeripheryBusFrequency(4000) ++
-  new chipyard.config.WithMemoryBusFrequency(4000) ++
+  new chipyard.config.WithSystemBusFrequency(500) ++
+  new chipyard.config.WithPeripheryBusFrequency(500) ++
+  new chipyard.config.WithMemoryBusFrequency(500) ++
+  new chipyard.config.WithFrontBusFrequency(50) ++
+  new chipyard.config.WithTileFrequency(1000, Some(1)) ++
+  new chipyard.config.WithTileFrequency(250, Some(0)) ++
 
-  new chipyard.config.WithFrontBusFrequency(4000 / 2) ++
-
-  new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
+  new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++
   new testchipip.WithAsynchronousSerialSlaveCrossing ++
+  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(
+    AsynchronousCrossing().depth,
+    AsynchronousCrossing().sourceSync) ++
 
   new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
   new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
 
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++
   new chipyard.config.AbstractConfig)