change dir structure

2019-03-07 14:18:24 -08:00
parent 419d41239f
commit 31e30b2ec7
4 changed files with 236 additions and 114 deletions
--- a/110
+++ b/110
@@ -0,0 +1,110 @@
+ROCKETCHIP_DIR=$(base_dir)/generators/rocket-chip
+TESTCHIP_DIR = $(base_dir)/generators/testchipip
+
+SCALA_VERSION=2.12.4
+SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
+
+SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
+
+lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
+
+PACKAGES=rocket-chip testchipip
+SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
+
+ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
+TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
+FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
+
+$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
+	$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
+	mkdir -p $(dir $@)
+	cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
+	touch $@
+
+build_dir=$(sim_dir)/generated-src
+
+CHISEL_ARGS ?=
+
+long_name=$(PROJECT).$(MODEL).$(CONFIG)
+
+FIRRTL_FILE  ?=$(build_dir)/$(long_name).fir
+ANNO_FILE    ?=$(build_dir)/$(long_name).anno.json
+VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
+HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
+SMEMS_FILE   ?=$(build_dir)/$(long_name).mems.v
+SMEMS_CONF   ?=$(build_dir)/$(long_name).mems.conf
+sim_dotf ?= $(build_dir)/sim_files.f
+
+REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
+
+# This should match whatever the commonSettings version is in build.sbt
+BARSTOOLS_VER=1.0
+TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar
+MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
+
+TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR)
+MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR)
+
+$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala)
+	cd $(base_dir) && $(SBT) "tapeout/assembly"
+
+$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala)
+	cd $(base_dir) && $(SBT) "barstools-macros/assembly"
+
+.PHONY: jars
+jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
+
+$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
+	cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
+
+$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
+	mkdir -p $(build_dir)
+	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
+
+$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
+	$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir)
+
+$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
+	$(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir)
+
+# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
+$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR)
+	$(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops
+
+regression-tests = \
+	rv64ud-v-fcvt \
+        rv64ud-p-fdiv \
+        rv64ud-v-fadd \
+        rv64uf-v-fadd \
+        rv64um-v-mul \
+        rv64mi-p-breakpoint \
+        rv64uc-v-rvc \
+        rv64ud-v-structural \
+        rv64si-p-wfi \
+        rv64um-v-divw \
+        rv64ua-v-lrsc \
+        rv64ui-v-fence_i \
+        rv64ud-v-fcvt_w \
+        rv64uf-v-fmin \
+        rv64ui-v-sb \
+        rv64ua-v-amomax_d \
+        rv64ud-v-move \
+        rv64ud-v-fclass \
+        rv64ua-v-amoand_d \
+        rv64ua-v-amoxor_d \
+        rv64si-p-sbreak \
+        rv64ud-v-fmadd \
+        rv64uf-v-ldst \
+        rv64um-v-mulh \
+        rv64si-p-dirty
+
+output_dir=$(sim_dir)/output
+
+$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
+	mkdir -p $(output_dir)
+	ln -sf $< $@
+
+.PHONY: clean-scala
+clean-scala:
+	rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
+
--- a/sims/verisim/Makefile
+++ b/sims/verisim/Makefile
@@ -1,43 +1,38 @@
-#########################################################################################
-# verilator makefile
-#########################################################################################
-
-#########################################################################################
-# general path variables
-#########################################################################################
 base_dir=$(abspath ../..)
 sim_dir=$(abspath .)

-#########################################################################################
-# include shared variables
-#########################################################################################
-include $(base_dir)/variables.mk
+PROJECT ?= example
+MODEL ?= TestHarness
+CONFIG ?= DefaultExampleConfig
+CFG_PROJECT ?= $(PROJECT)
+TB ?= TestDriver
+TOP ?= ExampleTop

-#########################################################################################
-# name of simulator (used to generate *.f arguments file)
-#########################################################################################
 sim_name = verilator

-#########################################################################################
-# vcs simulator types and rules
-#########################################################################################
-sim_prefix = simulator
-sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)
-sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug
+sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
+sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug

-.PHONY: default debug
 default: $(sim)
+
 debug: $(sim_debug)

-#########################################################################################
-# import other necessary rules and variables
-#########################################################################################
-include $(base_dir)/common.mk
-include $(sim_dir)/verilator.mk
+CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
+LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
+
+include $(base_dir)/Makefrag
+include $(sim_dir)/Makefrag-verilator
+
+sim_blackboxes = \
+  $(build_dir)/firrtl_black_box_resource_files.f
+
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+
+sim_vsrcs = \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE)

-#########################################################################################
-# verilator build paths and file names
-#########################################################################################
 model_dir = $(build_dir)/$(long_name)
 model_dir_debug = $(build_dir)/$(long_name).debug

@@ -47,11 +42,6 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h
 model_mk = $(model_dir)/V$(MODEL).mk
 model_mk_debug = $(model_dir_debug)/V$(MODEL).mk

-#########################################################################################
-# build makefile fragment that builds the verilator sim rules
-#########################################################################################
-LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
-
 $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
@@ -60,6 +50,10 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
 	touch $@

+$(sim): $(model_mk)
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
+
+
 $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name).debug
@@ -68,26 +62,25 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
 	touch $@

-#########################################################################################
-# invoke make to make verilator sim rules
-#########################################################################################
-$(sim): $(model_mk)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
-
 $(sim_debug): $(model_mk_debug)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk

-#########################################################################################
-# create a vcs vpd rule
-#########################################################################################
+$(output_dir)/%.out: $(output_dir)/% $(sim)
+	$(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
+
+$(output_dir)/%.run: $(output_dir)/% $(sim)
+	$(sim) +max-cycles=1000000 $< && touch $@
+
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	rm -f $@.vcd && mkfifo $@.vcd
 	vcd2vpd $@.vcd $@ > /dev/null &
-	$(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $<
+	$(sim_debug) -v$@.vcd +max-cycles=1000000 $<
+
+run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
+
+run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
+
+run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))

-#########################################################################################
-# general cleanup rule
-#########################################################################################
-.PHONY: clean
 clean: clean-scala
-	rm -rf $(build_dir) $(sim_prefix)-*
+	rm -rf generated-src ./simulator-*
--- a/sims/verisim/Makefrag-verilator
+++ b/sims/verisim/Makefrag-verilator
@@ -0,0 +1,34 @@
+# Build and install our own Verilator, to work around versionining issues.
+VERILATOR_VERSION=3.920
+VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
+INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
+$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
+	$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
+	touch $@
+
+$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
+	$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
+	touch $@
+
+$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
+	mkdir -p $(dir $@)
+	cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
+
+$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
+	rm -rf $(dir $@)
+	mkdir -p $(dir $@)
+	cat $^ | tar -xz --strip-components=1 -C $(dir $@)
+	touch $@
+
+verilator/verilator-$(VERILATOR_VERSION).tar.gz:
+	mkdir -p $(dir $@)
+	wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
+
+# Run Verilator to produce a fast binary to emulate this circuit.
+VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
+VERILATOR_FLAGS := --top-module $(MODEL) \
+	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
+	--output-split 20000 \
+	-Wno-STMTDLY --x-assign unique \
+	-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR"
--- a/sims/vsim/Makefile
+++ b/sims/vsim/Makefile
@@ -1,96 +1,81 @@
-#########################################################################################
-# vcs makefile
-#########################################################################################
-
-#########################################################################################
-# general path variables
-#########################################################################################
 base_dir=$(abspath ../..)
 sim_dir=$(abspath .)

-#########################################################################################
-# include shared variables
-#########################################################################################
-include $(base_dir)/variables.mk
+PROJECT ?= example
+MODEL ?= TestHarness
+CONFIG ?= DefaultExampleConfig
+CFG_PROJECT ?= $(PROJECT)
+TB ?= TestDriver
+TOP ?= ExampleTop

-#########################################################################################
-# name of simulator (used to generate *.f arguments file)
-#########################################################################################
 sim_name = vcs

-#########################################################################################
-# vcs simulator types and rules
-#########################################################################################
-sim_prefix = simv
-sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)
-sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug
+simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
+simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug

-.PHONY: default debug
-default: $(sim)
-debug: $(sim_debug)
+default: $(simv)

-#########################################################################################
-# import other necessary rules and variables
-#########################################################################################
-include $(base_dir)/common.mk
+debug: $(simv_debug)
+
+include $(base_dir)/Makefrag
+
+sim_blackboxes = \
+  $(build_dir)/firrtl_black_box_resource_files.f
+
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+
+sim_vsrcs = \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE)

-#########################################################################################
-# vcs binary and arguments
-#########################################################################################
 VCS = vcs -full64

-VCS_CC_OPTS = \
-	-CC "-I$(VCS_HOME)/include" \
+VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+	+rad +v2k +vcs+lic+wait \
+	+vc+list -CC "-I$(VCS_HOME)/include" \
 	-CC "-I$(RISCV)/include" \
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
-	$(RISCV)/lib/libfesvr.so
-
-VCS_NONCC_OPTS = \
-	+lint=all,noVCDE,noONGS,noUI \
-	-error=PCWM-L \
-	-timescale=1ns/10ps \
-	-quiet \
-	+rad \
-	+v2k \
-	+vcs+lic+wait \
-	+vc+list \
-	-f $(sim_blackboxes) \
-	-f $(sim_dotf) \
+	-f $(sim_blackboxes) -f $(sim_dotf) \
+	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
-	+incdir+$(build_dir) \
-	+define+CLOCK_PERIOD=1.0 \
-    $(sim_vsrcs) \
+	+incdir+$(generated_dir) \
+	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
 	+define+RANDOMIZE_MEM_INIT \
 	+define+RANDOMIZE_REG_INIT \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
 	+define+RANDOMIZE_INVALID_ASSIGN \
-	+libext+.v
+	+libext+.v \

-VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
+verilog: $(sim_vsrcs)

-#########################################################################################
-# vcs simulator rules
-#########################################################################################
-$(sim): $(sim_vsrcs) $(sim_dotf)
+$(simv): $(sim_vsrcs) $(sim_dotf)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	-debug_pp

-$(sim_debug) : $(sim_vsrcs) $(sim_dotf)
+$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	+define+DEBUG -debug_pp

-#########################################################################################
-# create a vcs vpd rule
-#########################################################################################
-$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
-	$(sim_debug) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $<
+$(output_dir)/%.out: $(output_dir)/% $(simv)
+	$(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
+
+$(output_dir)/%.run: $(output_dir)/% $(simv)
+	$(simv) +max-cycles=1000000 $< && touch $@
+
+$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
+	$(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $<
+
+run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
+
+run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
+
+run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
+
+clean:
+	rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h

-#########################################################################################
-# general cleanup rule
-#########################################################################################
 .PHONY: clean
-clean: clean-scala
-	rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h