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[ci skip] Update comments for FakePLLClockBinder

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This commit is contained in:
Jerry Zhao
2023-04-06 12:53:15 -07:00
parent 70643335d2
commit 32f0f83900
2 changed files with 6 additions and 2 deletions
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4
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -83,7 +83,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures what // The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource clockSelector.clockNode := pllClockSource

4
generators/chipyard/src/main/scala/example/FlatChipTop.scala
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@@ -43,7 +43,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures what // The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource clockSelector.clockNode := pllClockSource