Merge branch 'main' into uart-patch

.github/actions/create-conda-env/action.yml

@@ -11,7 +11,6 @@ runs:
           echo "Creating a conda environment for each toolchain with the toolchain installed"
           conda activate base
           conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools ./conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
-          conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
           conda deactivate
 
           echo "Add extra toolchain collateral + CIRCT to RISC-V install area"
@@ -25,14 +24,5 @@ runs:
               -x ./conda-reqs/circt.json \
               -g ${{ github.token }}
           conda deactivate
-          conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools
-          ./scripts/build-toolchain-extra.sh esp-tools -p $CONDA_PREFIX/esp-tools
-          ./tools/install-circt/bin/download-release-or-nightly-circt.sh \
-              -f circt-full-shared-linux-x64.tar.gz \
-              -i $CONDA_PREFIX \
-              -v version-file \
-              -x ./conda-reqs/circt.json \
-              -g ${{ github.token }}
-          conda deactivate
         fi
       shell: bash -leo pipefail {0}

.github/actions/run-tests/action.yml

@@ -23,7 +23,7 @@ runs:
     - name: Init submodules (since only the RTL is cached)
       run: |
         conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-${{ inputs.toolchain }}
-        ./scripts/init-submodules-no-riscv-tools.sh --force
+        ./scripts/init-submodules-no-riscv-tools.sh
       shell: bash -leo pipefail {0}
 
     # Note: You shouldn't need the other inputs since it shouldn't build RTL from scratch

.github/scripts/check-commit.sh

@@ -45,7 +45,7 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
 dir="generators"
 branches=("master" "main" "dev")
 search

.github/scripts/defaults.sh

@@ -29,11 +29,11 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
-grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
+grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
 grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
 
 # key value store to get the build strings
@@ -58,6 +58,8 @@ mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_F
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
+mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
+mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
@@ -67,6 +69,7 @@ mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
 mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
 mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
 mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
+mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
 mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
 
 mapping["constellation"]=" SUB_PROJECT=constellation"

.github/scripts/remote-do-rtl-build.sh

@@ -15,7 +15,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
 source $SCRIPT_DIR/defaults.sh
 
 cd $REMOTE_CHIPYARD_DIR
-./scripts/init-submodules-no-riscv-tools.sh --force
+./scripts/init-submodules-no-riscv-tools.sh
 
 # Constellation can run without espresso, but this improves
 # elaboration time drastically

.github/scripts/remote-run-firesim-scala-tests.sh

@@ -11,7 +11,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
 source $SCRIPT_DIR/defaults.sh
 
 cd $REMOTE_CHIPYARD_DIR
-./scripts/init-submodules-no-riscv-tools.sh --force
+./scripts/init-submodules-no-riscv-tools.sh
 
 # Run Firesim Scala Tests
 export FIRESIM_ENV_SOURCED=1

.github/scripts/run-tests.sh

@@ -118,6 +118,14 @@ case $1 in
         make -C $LOCAL_CHIPYARD_DIR/tests
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+cflush_addr=0x2010200"
         ;;
+    chipyard-symmetric)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
+        ;;
+    chipyard-llcchiplet)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;

.github/workflows/chipyard-full-flow.yml

@@ -83,7 +83,7 @@ jobs:
           eval "$(conda shell.bash hook)"
           mkdir ${{ env.JAVA_TMP_DIR }}
           export MAKEFLAGS="-j32"
-          ./build-setup.sh -f -v
+          ./build-setup.sh -v
 
   run-cfg-finder:
     name: run-cfg-finder

.github/workflows/chipyard-run-tests.yml

@@ -377,7 +377,7 @@ jobs:
       - name: Build Gemmini FireMarshal
         run: |
           conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
-          cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force
+          cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh
           cd ${{ github.workspace }} && source ./scripts/fix-open-files.sh
           git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh
           cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json
@@ -708,6 +708,52 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-tethered"
 
+  chipyard-symmetric-run-tests:
+    name: chipyard-symmetric-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-symmetric"
+
+  chipyard-llcchiplet-run-tests:
+    name: chipyard-llcchiplet-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-llcchiplet"
+
   chipyard-sha3-run-tests:
     name: chipyard-sha3-run-tests
     needs: prepare-chipyard-accels
@@ -1071,6 +1117,8 @@ jobs:
             chipyard-spiflashwrite-run-tests,
             chipyard-manyperipherals-run-tests,
             chipyard-tethered-run-tests,
+            chipyard-symmetric-run-tests,
+            chipyard-llcchiplet-run-tests,
             chipyard-sha3-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,

.github/workflows/update-circt.yml

@@ -16,7 +16,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Update CIRCT
-        uses: circt/update-circt@v1.0.0
+        uses: circt/update-circt@v1
         with:
           user: 'bartender'
           email: 'firesimchipyard@gmail.com'

.gitmodules

@@ -1,10 +1,10 @@
-[submodule "rocket-chip"]
+[submodule "generators/rocket-chip"]
 	path = generators/rocket-chip
 	url = https://github.com/chipsalliance/rocket-chip.git
-[submodule "testchipip"]
+[submodule "generators/testchipip"]
 	path = generators/testchipip
 	url = https://github.com/ucb-bar/testchipip.git
-[submodule "barstools"]
+[submodule "tools/barstools"]
 	path = tools/barstools
 	url = https://github.com/ucb-bar/barstools.git
 [submodule "tools/torture"]
@@ -13,9 +13,6 @@
 [submodule "generators/boom"]
 	path = generators/boom
 	url = https://github.com/riscv-boom/riscv-boom.git
-[submodule "generators/sifive-blocks"]
-	path = generators/sifive-blocks
-	url = https://github.com/chipsalliance/rocket-chip-blocks.git
 [submodule "generators/hwacha"]
 	path = generators/hwacha
 	url = https://github.com/ucb-bar/hwacha.git
@@ -25,9 +22,6 @@
 [submodule "generators/icenet"]
 	path = generators/icenet
 	url = https://github.com/firesim/icenet.git
-[submodule "generators/block-inclusivecache-sifive"]
-	path = generators/sifive-cache
-	url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
 [submodule "tools/dsptools"]
 	path = tools/dsptools
 	url = https://github.com/ucb-bar/dsptools.git
@@ -64,6 +58,9 @@
 [submodule "software/nvdla-workload"]
 	path = software/nvdla-workload
 	url = https://github.com/ucb-bar/nvdla-workload.git
+[submodule "software/baremetal-ide"]
+	path = software/baremetal-ide
+	url = https://github.com/ucb-bar/Baremetal-IDE.git
 [submodule "generators/riscv-sodor"]
 	path = generators/riscv-sodor
 	url = https://github.com/ucb-bar/riscv-sodor.git
@@ -145,3 +142,12 @@
 [submodule "toolchains/riscv-tools/riscv-spike-devices"]
 	path = toolchains/riscv-tools/riscv-spike-devices
 	url = https://github.com/ucb-bar/spike-devices.git
+[submodule "generators/rocket-chip-blocks"]
+	path = generators/rocket-chip-blocks
+	url = https://github.com/chipsalliance/rocket-chip-blocks.git
+[submodule "generators/rocket-chip-inclusive-cache"]
+	path = generators/rocket-chip-inclusive-cache
+	url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
+[submodule "tools/circt"]
+	path = tools/circt
+	url = https://github.com/llvm/circt.git

.readthedocs.yml

@@ -9,4 +9,4 @@ sphinx:
     configuration: docs/conf.py
 
 conda:
-    environment: conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+    environment: conda-reqs/docs.yaml

CHANGELOG.md

@@ -2,6 +2,101 @@
 
 This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
 
+## [1.11.0] - 2024-1-22
+
+Adds Ubuntu support for firemarshal, multi-chiptop configuration for chiplets, caliptra accelerator, spike-cosim.
+
+## Added
+- Provide example of tethered-config simulation with MultiHarnessBinders (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1484)
+- Add release note automation (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1548)
+- Improve peripheral config binders (Reapply #1511) (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1527)
+- UPF Generation (by @sriramsridhar23 in https://github.com/ucb-bar/chipyard/pull/1347)
+- Improve: SiFive peripheral device doumentation (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1578)
+- Bump to latest rocket-chip | integrated fixed-point | pull in stage/phase (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1577)
+- Enable precommit | Format files (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1585)
+- KLayout section of Sky130+OpenROAD tutorial (by @nayiri-k in https://github.com/ucb-bar/chipyard/pull/1514)
+- Added useful "Build script exited at step X" errors for each step in build-setup.sh (by @JL102 in https://github.com/ucb-bar/chipyard/pull/1614)
+- Adds support for Digilent Nexys Video FPGA board. (by @milovanovic in https://github.com/ucb-bar/chipyard/pull/1616)
+- Add NarrowRocketCache config fragment (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1603)
+- Add Caliptra AES256 ECB engine as RoCC accelerator (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1642)
+- Support using HarnessBinders without IOBinders (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1636)
+- Add Bringup on Arty100T config, using PMOD-gpio for ser-tl (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1657)
+- Install uart_tsi utility as part of build-toolchain-extra (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1670)
+- Add spike devices (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1692)
+- Bump testchipip to support multi-serial-tl (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1630)
+- ADD: bump fpga-shell (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1703)
+- Add UART device/JTAG to Arty100T default design (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1712)
+- Add generators/ submodule status check to all Make targets (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1718)
+- Add clearer --skip flags to build-setup (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1724)
+- Add Baremetal IDE support (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1534)
+- ADD: add information on Baremetal-IDE in docs (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1730)
+- Support clustered-cores (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1629)
+- Add debug clock tap port to all default designs (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1697)
+- Add support for symmetric serial-tilelink (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1716)
+- Add Chip ID Pin and Port (by @schwarz-em in https://github.com/ucb-bar/chipyard/pull/1721)
+- FastSimRocketConfig with no TLMonitors (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1752)
+- Use lean conda for faster initial setup (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1750)
+- Add BroadcastCoherence rocket config (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1755)
+
+## Changed
+- Bump FireMarshal (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1556)
+- Bump spike | support M-mode only cosim (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1530)
+- Bump to chisel3.6 (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1531)
+- Replace Dromajo FireSim bridge with Cospike (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1588)
+- Add PortAPI between IO and Harness blocks (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1610)
+- REFACTOR: change bootaddr register address and PC reset vector address (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1605)
+- REFACTOR: rename arty35t explicitly (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1682)
+- Add HasHarnessInstantiators into MultiHarnessBinder (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1674)
+- Install CIRCT out of Conda (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1675)
+- [cd] Bump CIRCT from firtool-1.58.0 to firtool-1.60.0 (copy #1688) (by @mergify[bot] in https://github.com/ucb-bar/chipyard/pull/1689)
+- Bump constellation with improved TL-noc (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1633)
+- Update testchipip imports with new testchipip organization (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1710)
+- CHANGE: Set scratchpad as default config (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1719)
+- Rename blocks/cache submodules to match new chipsalliance ownership (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1726)
+- Rename timeout_cycles to TIMEOUT_CYCLES to match convention (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1706)
+- [cd] Bump CIRCT from firtool-1.60.0 to firtool-1.61.0 (copy #1691) (by @mergify[bot] in https://github.com/ucb-bar/chipyard/pull/1699)
+- Bump tcip/barf/marshal/fsim (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1748)
+- Remove skip-validate option (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1749)
+- Add .gitignore for Embench Build Folder (by @vighneshiyer in https://github.com/ucb-bar/chipyard/pull/1754)
+
+## Fixed
+- Bump lockfiles | Force user-installed conda during conda-lock (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1555)
+- Fix FIFO-fixing for PRCI bus (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1563)
+- Fix VCU118 freq adjustment configs (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1597)
+- Fix Arty100T verilog build (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1608)
+- Make scripts/insert-includes.py use Python from conda env (by @hansungk in https://github.com/ucb-bar/chipyard/pull/1615)
+- Fix icenet-loopback clock and reset domain (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1612)
+- Bump FireMarshal for linux rng init fix (by @raghav-g13 in https://github.com/ucb-bar/chipyard/pull/1620)
+- Bump barstools (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1625)
+- [vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1631)
+- Fix regex for similar module names that are uniquified (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1640)
+- Rebuild `jar`s when `sv`/`v` files are changed + Add documentation on blackboxes (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1639)
+- Use TARGET instead of PREFIX in /tests Makefile(s) (by @raghav-g13 in https://github.com/ucb-bar/chipyard/pull/1647)
+- Fix IO direction for host Serial-TL port (by @ethanwu10 in https://github.com/ucb-bar/chipyard/pull/1654)
+- More robust env.sh | Fix conda activate if in subshell (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1653)
+- Always generate MFC Blackbox filelist (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1668)
+- Remove references to ENABLE_YOSYS (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1695)
+- FIX: fix vcu118 sd card frequency (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1685)
+- FIX: fix conda-lock version, >1.4.0 does not work! (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1714)
+- docs: correct to TOP_MACROCOMPILER_MODE (by @oharboe in https://github.com/ucb-bar/chipyard/pull/1744)
+- Use non-lock-file conda requirements in RTD (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1742)
+- Fix GCD MMIO example (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1753)
+
+## Removed
+- Remove pre-commit from env.sh (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1587)
+- Remove Dromajo (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1598)
+- Remove MultiClockHarnessAXIMem (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1601)
+
+## Uncategorized
+- Documentation: Change "don't use Windows" to "if using Windows, use WSL" (by @JL102 in https://github.com/ucb-bar/chipyard/pull/1572)
+- docs: Add info on chipyard's tests directory and how to do multithreading in RTL simulations (by @JL102 in https://github.com/ucb-bar/chipyard/pull/1646)
+- Reduce CDE lookups for IOBinders (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1720)
+- Update deprecated APIs to prepare for Chisel 5 (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1723)
+- Allow sed override in uniquify-module-names.py (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1729)
+- Update deprecated/unused Chisel APIs (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1743)
+
+**Full Changelog:** https://github.com/ucb-bar/chipyard/compare/1.10.0...main
+
 ## [1.10.0] - 2023-6-16
 
 Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop. FireSim bumped with new local FPGA support: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims.

build.sbt

@@ -95,7 +95,7 @@ lazy val chiselSettings = Seq(
 
 // -- Rocket Chip --
 
-lazy val hardfloat = freshProject("hardfloat", rocketChipDir / "hardfloat/hardfloat")
+lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
   .settings(chiselSettings)
   .dependsOn(midasTargetUtils)
   .settings(commonSettings)
@@ -141,12 +141,12 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
 
 lazy val testchipip = (project in file("generators/testchipip"))
-  .dependsOn(rocketchip, sifive_blocks)
+  .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
 lazy val chipyard = (project in file("generators/chipyard"))
-  .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+  .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
@@ -180,7 +180,7 @@ lazy val fft_generator = (project in file("generators/fft-generator"))
   .settings(commonSettings)
 
 lazy val tracegen = (project in file("generators/tracegen"))
-  .dependsOn(testchipip, rocketchip, sifive_cache, boom)
+  .dependsOn(testchipip, rocketchip, rocketchip_inclusive_cache, boom)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -279,12 +279,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
+lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sifive_cache = (project in file("generators/sifive-cache"))
+lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache"))
   .settings(
     commonSettings,
     Compile / scalaSource := baseDirectory.value / "design/craft")
@@ -304,7 +304,7 @@ lazy val firechip = (project in file("generators/firechip"))
     Test / testOptions += Tests.Argument("-oF")
   )
 lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
-  .dependsOn(rocketchip, sifive_blocks)
+  .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 

common.mk

@@ -57,7 +57,8 @@ HELP_COMMANDS += \
 "   firrtl                      = generate intermediate firrtl files from chisel elaboration" \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
-"   find-config-fragments       = list all config. fragments"
+"   find-config-fragments       = list all config. fragments" \
+"   check-submodule-status      = check that all submodules in generators/ have been initialized"
 
 #########################################################################################
 # include additional subproject make fragments
@@ -83,6 +84,8 @@ endif
 # Returns a list of files in directories $1 with *any* of the file extensions in $2
 lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type)))
 
+CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep ^-
+
 SCALA_EXT = scala
 VLOG_EXT = sv v
 CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
@@ -119,6 +122,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 # compile scala jars
 #########################################################################################
 $(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
+	$(CHECK_SUBMODULES_COMMAND)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
 
@@ -189,7 +193,7 @@ SFC_MFC_TARGETS = \
 	$(GEN_COLLATERAL_DIR)
 
 SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
-MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
+MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
 
 # DOC include start: FirrtlCompiler
 # There are two possible cases for this step. In the first case, SFC
@@ -294,10 +298,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &:  $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
 TOP_MACROCOMPILER_MODE ?= --mode synflops
 $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
 	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
+	touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR)
 
 MODEL_MACROCOMPILER_MODE = --mode synflops
-$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
+$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF)
 	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
+	touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR)
 
 ########################################################################################
 # remove duplicate files and headers in list of simulation file inputs
@@ -365,14 +371,27 @@ run-binary: check-binary $(BINARY).run
 run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
 
 %.run: %.check-exists $(SIM_PREREQ) | $(output_dir)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(VERBOSE_FLAGS) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
 # run simulator as fast as possible (no insn disassembly)
 run-binary-fast: check-binary $(BINARY).run.fast
 run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
 
 %.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* </dev/null | tee $(call get_sim_out_name,$*).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null | tee $(call get_sim_out_name,$*).log)
 
 # run simulator with as much debug info as possible
 run-binary-debug: check-binary $(BINARY).run.debug
@@ -380,7 +399,15 @@ run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))
 
 %.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
 	if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
-	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(VERBOSE_FLAGS) \
+		$(call get_waveform_flag,$(call get_sim_out_name,$*)) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
 run-fast: run-asm-tests-fast run-bmark-tests-fast
 
@@ -451,9 +478,24 @@ find-config-fragments:
 help:
 	@for line in $(HELP_LINES); do echo "$$line"; done
 
+#########################################################################################
+# Check submodule status
+#########################################################################################
+
+.PHONY: check-submodule-status
+check-submodule-status:
+	$(CHECK_SUBMODULES_COMMAND)
+
 #########################################################################################
 # Implicit rule handling
 #########################################################################################
 # Disable all suffix rules to improve Make performance on systems running older
 # versions of Make
 .SUFFIXES:
+
+.PHONY: print-%
+# Print any variable and it's origin. This helps figure out where the
+# variable was defined and to distinguish between empty and undefined.
+print-%:
+	@echo "$*=$($*)"
+	@echo "Origin is: $(origin $*)"

conda-reqs/chipyard-base.yaml

@@ -0,0 +1,35 @@
+channels:
+    - ucb-bar
+    - conda-forge
+    - litex-hub
+    - nodefaults
+
+platforms:
+    - linux-64
+
+dependencies:
+    # https://conda-forge.org/feedstock-outputs/
+    #   filterable list of all conda-forge packages
+    # https://conda-forge.org/#contribute
+    #   instructions on adding a recipe
+    # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
+    #   documentation on package_spec syntax for constraining versions
+    - gcc<12
+    - gxx<12
+    - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
+    - conda-gcc-specs
+    - binutils
+
+    # misc
+    - autoconf
+    - coreutils
+    - jq
+    - pip
+    - make
+    - git
+
+    - sbt
+    - openjdk=20
+    - dtc
+    - verilator==5.022
+    - conda-lock=1.4

conda-reqs/chipyard-extended.yaml

@@ -8,14 +8,6 @@ platforms:
     - linux-64
 
 dependencies:
-    # https://conda-forge.org/feedstock-outputs/
-    #   filterable list of all conda-forge packages
-    # https://conda-forge.org/#contribute
-    #   instructions on adding a recipe
-    # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
-    #   documentation on package_spec syntax for constraining versions
-
-
     # handy tool for introspecting package relationships and file ownership
     # see https://github.com/rvalieris/conda-tree
     - conda-tree
@@ -23,21 +15,9 @@ dependencies:
     # bundle FireSim driver with deps into installer shell-script
     - constructor
 
-    - gcc<13
-    - gxx<13
-    - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
-    - conda-gcc-specs
-    - binutils
-
-    # firtool handled outside of conda
-
     # misc
-    - autoconf
     - pre-commit
     - readline
-    - coreutils
-    - jq
-    - pip
 
     # firemarshal deps
     - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock
@@ -67,9 +47,7 @@ dependencies:
     - findutils
     - lzop
 
-    - make
     - bash-completion
-    - sbt
     - ca-certificates
     - mosh
     - gmp
@@ -77,8 +55,6 @@ dependencies:
     - mpc
     - zlib
     - vim
-    - git
-    - openjdk
     - gengetopt
     - libffi
     - expat
@@ -87,12 +63,6 @@ dependencies:
     - cmake
     - graphviz
     - expect
-    - dtc
-    - verilator==5.008
-    - screen
-    - elfutils
-    - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
-    - conda-lock=1.4
 
     # clang-format for driver coding style enforcement.
     - clang-format
@@ -104,18 +74,14 @@ dependencies:
     - pip:
         - hammer-vlsi[asap7]==1.2.0
 
-    # doc requirements
-    - sphinx
-    - pygments
-    - sphinx-autobuild
-    - sphinx_rtd_theme
-    - docutils
-
     # firesim python packages
     # While it is possible to install using pip after creating the
     # conda environment, pip's dependency resolution can conflict with
     # conda and create broken environments.  It's best to use the conda
     # packages so that the environment is consistent
+    - screen
+    - elfutils
+    - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
     - colorama
     - argcomplete
     - python-graphviz

conda-reqs/circt.json

@@ -1,3 +1,3 @@
 {
-  "version": "firtool-1.60.0"
+  "version": "firtool-1.66.0"
 }

conda-reqs/docs.yaml

@@ -0,0 +1,23 @@
+channels:
+    - ucb-bar
+    - conda-forge
+    - litex-hub
+    - nodefaults
+
+platforms:
+    - linux-64
+
+dependencies:
+    # https://conda-forge.org/feedstock-outputs/
+    #   filterable list of all conda-forge packages
+    # https://conda-forge.org/#contribute
+    #   instructions on adding a recipe
+    # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
+    #   documentation on package_spec syntax for constraining versions
+
+    # doc requirements
+    - sphinx
+    - pygments
+    - sphinx-autobuild
+    - sphinx_rtd_theme
+    - docutils

docs/Advanced-Concepts/Chip-Communication.rst

@@ -198,25 +198,3 @@ bringup design).
     :language: scala
     :start-after: DOC include start: TetheredChipLikeRocketConfig
     :end-before: DOC include end: TetheredChipLikeRocketConfig
-
-Softcore-driven Bringup Setup of the Example Test Chip after Tapeout
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-.. warning::
-   Bringing up test chips with a FPGA softcore  as described here is discouraged.
-   An alternative approach using the FPGA to "bridge" between a host computer and the test chip is the preferred approach.
-
-Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link.
-For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC).
-This RISC-V soft-core would serve as the host of the test that will run on the DUT.
-This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``TSIToTileLink`` / ``TLSerdesser`` programmed on the FPGA.
-Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT
-(like an FMC cable or a set of wires connecting FPGA outputs to the DUT board).
-Similar to simulation, if the chip requests offchip memory, it can then send the transaction back over the serial-link.
-Then the request can be serviced by the FPGA DRAM.
-The following image shows this flow:
-
-.. image:: ../_static/images/chip-bringup.png
-
-In fact, this exact type of bringup setup is what the following section discusses:
-:ref:_legacy-vcu118-bringup.

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -53,9 +53,9 @@ System Components:
 **icenet**
   A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
 
-**sifive-blocks**
-  System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
-  These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
+**rocket-chip-blocks**
+  System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
+  Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
 
 **AWL (Analog Widget Library)**
   Digital components required for integration with high speed serial links.
@@ -106,6 +106,9 @@ Software
   FireMarshal is the default workload generation tool that Chipyard uses to create software to run on its platforms.
   See :ref:`fire-marshal` for more information.
 
+**Baremetal-IDE**
+  Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program development. See `Tutorial <https://ucb-bar.gitbook.io/chipyard/baremetal-ide/getting-started-with-baremetal-ide/>`_ for more information.
+
 Sims
 -------------------------------------------
 

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -15,8 +15,8 @@ Running on AWS EC2 with FireSim
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 If you plan on using Chipyard alongside FireSim on AWS EC2 instances, you should refer to the :fsim_doc:`FireSim documentation <>`.
-Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Initial-Setup/index.html>`
-section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
+Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/index.html>`
+section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
 At that point, instead of cloning FireSim you can clone Chipyard by following :ref:`Chipyard-Basics/Initial-Repo-Setup:Setting up the Chipyard Repo`.
 
 Default Requirements Installation

docs/Customization/Boot-Process.rst

@@ -74,6 +74,6 @@ mode, thus starting userspace execution.
 The easiest way to build a BBL image that boots Linux is to use the FireMarshal
 tool that lives in the `firesim-software <https://github.com/firesim/firesim-software>`_
 repository. Directions on how to use FireMarshal can be found in the
-:fsim_doc:`FireSim documentation <Advanced-Usage/FireMarshal/index.html>`.
+:fsim_doc:`FireSim documentation <Advanced-Usage/Workloads/FireMarshal.html>`.
 Using FireMarshal, you can add custom kernel configurations and userspace software
 to your workload.

docs/Customization/Custom-Chisel.rst

@@ -59,7 +59,7 @@ should look something like this:
 .. code-block:: scala
 
     lazy val chipyard = (project in file("generators/chipyard"))
-        .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+        .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
             sha3, dsptools, `rocket-dsp-utils`,
             gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
             yourproject, // <- added to the middle of the list for simplicity

docs/Customization/Incorporating-Verilog-Blocks.rst

@@ -99,10 +99,16 @@ Instantiating the BlackBox and Defining MMIO
 
 Next, we must instantiate the blackbox. In order to take advantage of
 diplomatic memory mapping on the system bus, we still have to
-integrate the peripheral at the Chisel level by mixing
-peripheral-specific traits into a ``TLRegisterRouter``. The ``params``
-member and ``HasRegMap`` base trait should look familiar from the
-previous memory-mapped GCD device example.
+integrate the peripheral at the Chisel level by instantiating a LazyModule wrapper
+that instantiates a TileLink RegisterNode.
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
+    :language: scala
+    :start-after: DOC include start: GCD router
+    :end-before: DOC include end: GCD router
+
+Within the LazyModule, the ``regmap`` function can be called to attach wires and
+registers to the MMIO port.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
     :language: scala

docs/Customization/Keys-Traits-Configs.rst

@@ -40,12 +40,12 @@ Top-level traits specify that the ``DigitalTop`` has been parameterized to read
 
 Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``DigitalTop`` being used by Chipyard.
 
-Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``DigitalTop`` to instantiate an additional port and concretely connect it to the GCD module.
+Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
     :language: scala
     :start-after: DOC include start: GCD lazy trait
-    :end-before: DOC include end: GCD imp trait
+    :end-before: DOC include end: GCD lazy trait
 
 These traits are added to the default ``DigitalTop`` in Chipyard.
 

docs/Customization/MMIO-Peripherals.rst

@@ -3,14 +3,15 @@
 MMIO Peripherals
 ==================
 
-The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/example/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters.
+The easiest way to create a MMIO peripheral is to follow the GCD TileLink MMIO example. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/example/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters.
 
-To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL.
+To create a MMIO-mapped peripheral, you will need to specify a ``LazyModule`` wrapper containing the TileLink port as a Diplomacy Node, as well as an internal ``LazyModuleImp`` class that defines the MMIO's implementation and any non-TileLink I/O.
 
 For this example, we will show how to connect a MMIO peripheral which computes the GCD.
 The full code can be found in ``generators/chipyard/src/main/scala/example/GCD.scala``.
 
-In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDModule`` class only creates the registers and hooks them up using ``regmap``.
+In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDTL`` and ``GCDAXI4`` classes are the ``LazyModule`` classes which construct the TileLink or AXI4 ports, wrapping the inner ``GCDMMIOChiselModule``.
+The ``node`` object is a Diplomacy node, which connects the peripheral to the Diplomacy interconnect graph.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
     :language: scala
@@ -19,8 +20,9 @@ In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
     :language: scala
-    :start-after: DOC include start: GCD instance regmap
-    :end-before: DOC include end: GCD instance regmap
+    :start-after: DOC include start: GCD router
+    :end-before: DOC include end: GCD router
+
 
 Advanced Features of RegField Entries
 -------------------------------------
@@ -41,15 +43,31 @@ triggering the GCD algorithm when ``y`` is written. Therefore, the
 algorithm is set up by first writing ``x`` and then performing a
 triggering write to ``y``. Polling can be used for status checks.
 
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
+    :language: scala
+    :start-after: DOC include start: GCD instance regmap
+    :end-before: DOC include end: GCD instance regmap
+
+.. note::
+   In older versions of Chipyard and Rocket-Chip, a ``TLRegisterRouter`` abstrat
+   class was used to abstract away the construction of the ``TLRegisterNode`` and
+   ``LazyModule`` classes necessary to construct MMIO peripherals. This was removed,
+   in favor of requiring users to explicitly construct the necessary classes.
+
+   This matches more closely how standard ``Modules`` and ``LazyModules`` are
+   constructed, making it clearer how a MMIO peripheral fits into the ``Module``
+   and ``LazyModule`` design patterns.
+
 
 Connecting by TileLink
 ----------------------
 
-Once you have these classes, you can construct the final peripheral by extending the ``TLRegisterRouter`` and passing the proper arguments.
-The first set of arguments determines where the register router will be placed in the global address map and what information will be put in its device tree entry.
-The second set of arguments is the IO bundle constructor, which we create by extending ``TLRegBundle`` with our bundle trait.
-The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait.
-Notice how we can create an analogous AXI4 version of our peripheral.
+The key to connecting to the TileLink Diplomatic graph is the construction of the TileLink node for this peripheral.
+In this case, since the peripheral acts as a manager of some register-mapped address space, it uses the ``TLRegisterNode`` object.
+The parameters to the ``TLRegisterNode`` object specify the size of the managed space, the base address, and the port width.
+
+Within the register-mapped peripheral, the control registers can be mapped using the ``node.regmap`` function, as described above.
+A similar procedure is followed for both AXI4 and TileLin peripherals.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
     :language: scala
@@ -62,30 +80,18 @@ Top-level Traits
 ----------------
 
 After creating the module, we need to hook it up to our SoC.
-Rocket Chip accomplishes this using the cake pattern.
-This basically involves placing code inside traits.
-In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait and a module implementation trait.
-
-The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated.
-For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar.
+The ``LazyModule`` abstract class containst the TileLink node representing the peripheral's I/O.
+For a simple memory-mapped peripheral, connecting the peripheral's TileLink node must be connected to the relevant bu.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
     :language: scala
     :start-after: DOC include start: GCD lazy trait
     :end-before: DOC include end: GCD lazy trait
 
-Note that the ``GCDTL`` class we created from the register router is itself a ``LazyModule``.
-Register routers have a TileLink node simply named "node", which we can hook up to the Rocket Chip bus.
-This will automatically add address map and device tree entries for the peripheral.
 Also observe how we have to place additional AXI4 buffers and converters for the AXI4 version of this peripheral.
 
-For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module.
-
-
-.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
-    :language: scala
-    :start-after: DOC include start: GCD imp trait
-    :end-before: DOC include end: GCD imp trait
+Peripherals which expose I/O can use `InModuleBody` to punch their I/O to the `DigitalTop` module.
+In this example, the GCD module's ``gcd_busy`` signal is exposed as a I/O of DigitalTop.
 
 Constructing the DigitalTop and Config
 --------------------------------------

docs/Customization/Memory-Hierarchy.rst

@@ -46,17 +46,17 @@ agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, but
 a network-on-chip-based implementation can be generated using Constellation.
 See :ref:`Customization/NoC-SoCs:SoCs with NoC-based Interconnects` for more.
 
-The SiFive L2 Cache
--------------------
+The Inclusive Last-Level Cache
+---------------------------------
 
-The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's
+The default ``RocketConfig`` provided in the Chipyard example project uses the Rocket-Chip
 InclusiveCache generator to produce a shared L2 cache. In the default
 configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way
 set-associativity. However, you can change these parameters to obtain your
 desired cache configuration. The main restriction is that the number of ways
 and the number of banks must be powers of 2.
 
-Refer to the ``CacheParameters`` object defined in sifive-cache for
+Refer to the ``CacheParameters`` object defined in ``rocket-chip-inclusive-cache`` for
 customization options.
 
 The Broadcast Hub

docs/Generators/Hwacha.rst

@@ -5,7 +5,7 @@ The Hwacha project is developing a new vector architecture for future computer s
 The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven
 The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
 
-For more information on the Hwacha project, please visit the `Hwacha website <http://hwacha.org/>`__.
+For more information on the Hwacha project, please visit the `Hwacha website <https://bar.eecs.berkeley.edu/projects/hwacha.html>`__ or search for "Krste Asanovic Hwacha" on Google Scholar for publications.
 
 To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache).
 

docs/Generators/Rocket-Chip-Generators.rst

@@ -1,19 +1,19 @@
-SiFive Generators
-==================
+Rocket-Chip Generators
+======================
 
-Chipyard includes several open-source generators developed and maintained by `SiFive <https://www.sifive.com/>`__.
-These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
+Chipyard includes several open-source generators developed by `SiFive <https://www.sifive.com/>`__, and now openly maintained as part of Chips Alliance.
+These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``.
 
 Last-Level Cache Generator
 -----------------------------
 
-``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
+``rocket-chip-inclusive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
 To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
 
 
 Peripheral Devices Overview
 ----------------------------
-``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
+``rocket-chip-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
 
 These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
 All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
@@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example:
 General Purpose I/Os (GPIO) Device
 ----------------------------------
 
-GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
+GPIO device is a periphery device provided by ``rocket-chip-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
 
 
 GPIO main features
@@ -78,7 +78,7 @@ Including GPIO in the SoC
 Universal Asynchronous Receiver/Transmitter (UART) Device
 ----------------------------------------------------------
 
-UART device is a periphery device provided by ``sifive-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
+UART device is a periphery device provided by ``rocket-chip-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
 
 
 UART main features
@@ -125,7 +125,7 @@ Including UART in the SoC
 Inter-Integrated Circuit (I2C) Interface Device
 -------------------------------------------------
 
-I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
+I2C device is a periphery device provided by ``rocket-chip-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
 
 
 I2C main features
@@ -169,7 +169,7 @@ Including I2C in the SoC
 Serial Peripheral Interface (SPI) Device
 -------------------------------------------------
 
-SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
+SPI device is a periphery device provided by ``rocket-chip-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
 
 The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
 

docs/Generators/Rocket-Chip.rst

@@ -1,8 +1,8 @@
 Rocket Chip
 ===========
 
-Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
-`SiFive <https://www.sifive.com>`__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
+Rocket Chip generator is an SoC generator developed at Berkeley and SiFive, and now maintained openly in Chips Alliance.
+Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
 
 `Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
 Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip

docs/Generators/Rocket.rst

@@ -1,7 +1,7 @@
 Rocket Core
 ====================================
 
-`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive <https://www.sifive.com/>`__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
+`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and `SiFive <https://www.sifive.com/>`__, and now maintained by Chips Alliance. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
 
 The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
 It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.

docs/Generators/TestChipIP.rst

@@ -92,3 +92,15 @@ The SPI flash model is a device that models a simple SPI flash device. It curren
 only supports single read, quad read, single write, and quad write instructions. The
 memory is backed by a file which is provided using ``+spiflash#=<NAME_OF_FILE>``,
 where ``#`` is the SPI flash ID (usually ``0``).
+
+Chip ID Pin
+---------------
+
+The chip ID pin sets the chip ID for the chip it is added to. This is most useful in 
+multi-chip configs. The pin value is driven by the chip ID value set in the harness 
+binder and the chip ID value can be read through MMIO at the address ``0x2000`` by default.
+
+The pin can be added to a system with the ``testchipip.soc.WithChipIdPin`` config. The pin
+width and MMIO address are parameterizable and can be set by passing ``ChipIdPinParams`` as an 
+argument to the config. The width can additionally be set using the ``testchipip.soc.WithChipIdPinWidth``
+config. 

docs/Generators/index.rst

@@ -26,7 +26,7 @@ so changes to the generators themselves will automatically be used when building
    Gemmini
    IceNet
    TestChipIP
-   SiFive-Generators
+   Rocket-Chip-Generators
    SHA3
    CVA6
    Ibex

docs/Prototyping/VCU118.rst

@@ -47,20 +47,6 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to
 This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``).
 For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`.
 
-(Legacy) Introduction to the Legacy Bringup Design
---------------------------------------------------
-
-.. warning::
-   The bringup VCU118 design described here is designed for old versions of Chipyard SoCs, pre-1.9.1.
-   The key difference is that these designs rely on a clock generated on-chip to synchronize the slow serialized-TileLink interface.
-   After Chipyard 1.9.1, the FPGA host is expected to pass the clock to the chip, instead of the other way around.
-   A new bringup solution will be developed for post-1.9.1 Chipyard designs.
-
-An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``.
-This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port).
-Extensions include another UART (connected over FMC), I2C (connected over FMC), miscellaneous GPIOS (can be connected to anything), and a TSI Host Widget.
-The TSI Host Widget is used to interact with the DUT from the prototype over a SerDes link (sometimes called the Low BandWidth InterFace - LBWIF) and provide access to a channel of the FPGA's DRAM.
-
 .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation.
     For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``.
     See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables.

docs/Simulation/FPGA-Accelerated-Simulation.rst

@@ -26,12 +26,14 @@ Finally, source the following environment at the root of the FireSim directory:
 
     cd sims/firesim
     # (Recommended) The default manager environment (includes env.sh)
-    source sourceme-manager.sh
+    source sourceme-manager.sh`
+    # Completing setup using the manager
+    firesim managerinit --platform f1
 
 .. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh``
 
 At this point you're ready to use FireSim with Chipyard. If you're not already
-familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
+familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
 and proceed with the rest of the tutorial.
 
 Running your Design in FireSim
@@ -47,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments:
 
 
 The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme.
-After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
+After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
 
 An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments.
 We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``.
@@ -59,3 +61,5 @@ We are using the same target (top) RTL, and only need to specify a new set of co
     :end-before: DOC include end: firesimconfig
 
 While this option seems to require the maintenance of additional configuration code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``)
+
+For more information on how to build your own hardware design on FireSim, please refer to :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Building-a-FireSim-AFI.html#building-your-own-hardware-designs-firesim-amazon-fpga-images>`.

docs/Simulation/Software-RTL-Simulation.rst

@@ -223,3 +223,29 @@ The ``VERILATOR_THREADS=<num>`` option enables the compiled Verilator simulator
 On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``NUMACTL=1`` to enable ``numactl``.
 By enabling this, you will use Chipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator-<name> <simulator-args>``.
 Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation).
+
+
+Speeding up your RTL Simulation by 2x!
+-----------------------------------------------
+
+There are many cases when your custom module interfaces with Tilelink (e.g., when you write a custom accelerator).
+Wrong interfaces with Tilelink can cause the SoC to hang and can be tricky to debug.
+To help deal with these situations, you can add hardware modules called Tilelink monitors into
+your SoC that will fire assertions when wrong Tilelink messages are sent.
+However, these modules can significantly slow down the speed of your RTL simulation.
+
+These modules are added to the SoC as a default and users have to manually
+remove these modules by adding the below line into your config.
+
+.. code-block:: scala
+
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+
+
+For instance:
+
+.. code-block:: scala
+
+  class FastRTLSimRocketConfig extends Config(
+    new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+    new chipyard.RocketConfig)

docs/TileLink-Diplomacy-Reference/NodeTypes.rst

@@ -134,7 +134,7 @@ to handle TileLink requests, it is usually much easier to use a register node.
 This type of node provides a ``regmap`` method that allows you to specify
 control/status registers and automatically generates the logic to handle the
 TileLink protocol. More information about how to use register nodes can be
-found in :ref:`TileLink-Diplomacy-Reference/Register-Router:Register Router`.
+found in :ref:`TileLink-Diplomacy-Reference/Register-Node:Register Node`.
 
 Identity Node
 -------------

docs/TileLink-Diplomacy-Reference/Register-Node.rst

@@ -1,4 +1,4 @@
-Register Router
+Register Node
 ===============
 
 Memory-mapped devices generally follow a common pattern. They expose a set
@@ -10,10 +10,7 @@ While designers can manually instantiate a manager node and write the logic
 for exposing registers themselves, it's much easier to use RocketChip's
 ``regmap`` interface, which can generate most of the glue logic.
 
-For TileLink devices, you can use the ``regmap`` interface by extending
-the ``TLRegisterRouter`` class, as shown in :ref:`mmio-accelerators`,
-or you can create a regular LazyModule and instantiate a ``TLRegisterNode``.
-This section will focus on the second method.
+For TileLink devices, you can use the ``regmap`` interface of the ``TLRegisterNode``.
 
 Basic Usage
 -----------
@@ -32,7 +29,7 @@ The default value is 4 bytes. The ``concurrency`` argument is the size of the
 internal queue for TileLink requests. By default, this value is 0, which means
 there will be no queue. This value must be greater than 0 if you wish to
 decoupled requests and responses for register accesses. This is discussed
-in :ref:`TileLink-Diplomacy-Reference/Register-Router:Using Functions`.
+in :ref:`TileLink-Diplomacy-Reference/Register-Node:Using Functions`.
 
 The main way to interact with the node is to call the ``regmap`` method, which
 takes a sequence of pairs. The first element of the pair is an offset from the
@@ -123,12 +120,12 @@ output for write.
 In order to use this variant, you need to set ``concurrency`` to a value
 larger than 0.
 
-Register Routers for Other Protocols
+Register Nodes for Other Protocols
 ------------------------------------
 
-One useful feature of the register router interface is that you can easily
+One useful feature of the register node interface is that you can easily
 change the protocol being used. For instance, in the first example in
-:ref:`TileLink-Diplomacy-Reference/Register-Router:Basic Usage`, you could simply change the ``TLRegisterNode`` to
+:ref:`TileLink-Diplomacy-Reference/Register-Node:Basic Usage`, you could simply change the ``TLRegisterNode`` to
 and ``AXI4RegisterNode``.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala

docs/TileLink-Diplomacy-Reference/index.rst

@@ -28,5 +28,5 @@ A detailed specification of the TileLink 1.7 protocol can be found on the
     NodeTypes
     Diplomacy-Connectors
     EdgeFunctions
-    Register-Router
+    Register-Node
     Widgets

docs/VLSI/Basic-Flow.rst

@@ -57,7 +57,7 @@ As in the rest of the Chipyard flows, we specify our SoC configuration using the
 However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module.
 Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on.
 The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly.
-By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
+By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``TOP_MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
 
 We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``.
 

fpga/Makefile

@@ -44,20 +44,6 @@ ifeq ($(SUB_PROJECT),vcu118)
 	FPGA_BRAND        ?= xilinx
 endif
 
-ifeq ($(SUB_PROJECT),bringup)
-	SBT_PROJECT       ?= fpga_platforms
-	MODEL             ?= BringupVCU118FPGATestHarness
-	VLOG_MODEL        ?= BringupVCU118FPGATestHarness
-	MODEL_PACKAGE     ?= chipyard.fpga.vcu118.bringup
-	CONFIG            ?= RocketBringupConfig
-	CONFIG_PACKAGE    ?= chipyard.fpga.vcu118.bringup
-	GENERATOR_PACKAGE ?= chipyard
-	TB                ?= none # unused
-	TOP               ?= ChipTop
-	BOARD             ?= vcu118
-	FPGA_BRAND        ?= xilinx
-endif
-
 ifeq ($(SUB_PROJECT),nexysvideo)
 	SBT_PROJECT       ?= fpga_platforms
 	MODEL             ?= NexysVideoHarness
@@ -137,7 +123,7 @@ include $(base_dir)/common.mk
 # copy from other directory
 #########################################################################################
 all_vsrcs := \
-	$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
+	$(base_dir)/generators/rocket-chip-blocks/vsrc/SRLatch.v
 
 #########################################################################################
 # vivado rules

fpga/src/main/scala/arty/Configs.scala

@@ -30,6 +30,7 @@ class WithArtyTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
+  new chipyard.config.WithControlBusFrequency(32) ++
   new testchipip.serdes.WithNoSerialTL ++
   new testchipip.soc.WithNoScratchpads
 )

fpga/src/main/scala/arty/HarnessBinders.scala

@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
 import chipyard.iobinders._
 
 class WithArtyDebugResetHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: DebugResetPort) => {
+  case (th: Arty35THarness, port: DebugResetPort, chipId: Int) => {
     th.dut_ndreset := port.io // Debug module reset
   }
 })
 
 class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: JTAGResetPort) => {
+  case (th: Arty35THarness, port: JTAGResetPort, chipId: Int) => {
     port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
   }
 })
 
 class WithArtyJTAGHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: JTAGPort) => {
+  case (th: Arty35THarness, port: JTAGPort, chipId: Int) => {
     val jtag_wire = Wire(new JTAGIO)
     jtag_wire.TDO.data := port.io.TDO
     jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
 })
 
 class WithArtyUARTHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: UARTPort) => {
+  case (th: Arty35THarness, port: UARTPort, chipId: Int) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       IOBUF(th.uart_rxd_out,  port.io.txd)
       port.io.rxd := IOBUF(th.uart_txd_in)

fpga/src/main/scala/arty100t/Configs.scala

@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}
 
 // don't use FPGAShell's DesignKey
 class WithNoDesignKey extends Config((site, here, up) => {
-  case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+  case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })
 
 // By default, this uses the on-board USB-UART for the TSI-over-UART link
@@ -58,5 +58,5 @@ class NoCoresArty100TConfig extends Config(
 class BringupArty100TConfig extends Config(
   new WithArty100TSerialTLToGPIO ++
   new WithArty100TTweaks(freqMHz = 50) ++
-  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialPhyParams(freqMHz=50)) ++
   new chipyard.ChipBringupHostConfig)

fpga/src/main/scala/arty100t/Harness.scala

@@ -5,12 +5,12 @@ import chisel3.util._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.prci._
 import freechips.rocketchip.subsystem.{SystemBusKey}
 
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
 
 import sifive.blocks.devices.uart._
@@ -76,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
     def referenceReset = dutClock.in.head._1.reset
     def success = { require(false, "Unused"); false.B }
 
+    childClock := harnessBinderClock
+    childReset := harnessBinderReset
+
     ddrOverlay.mig.module.clock := harnessBinderClock
     ddrOverlay.mig.module.reset := harnessBinderReset
     ddrBlockDuringReset.module.clock := harnessBinderClock

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.arty100t
 
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction}
 
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
@@ -19,9 +18,10 @@ import sifive.fpgashells.clocks._
 import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
+import testchipip.serdes._
 
 class WithArty100TUARTTSI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
+  case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
     harnessIO <> port.io.uart
@@ -44,7 +44,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
 
 
 class WithArty100TDDRTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: TLMemPort) => {
+  case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val bundles = artyTh.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
@@ -55,47 +55,58 @@ class WithArty100TDDRTL extends HarnessBinder({
 
 // Uses PMOD JA/JB
 class WithArty100TSerialTLToGPIO extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+  case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
     harnessIO <> port.io
-    val clkIO = IOPin(harnessIO.clock)
-    val packagePinsWithPackageIOs = Seq(
-      ("G13", clkIO),
-      ("B11", IOPin(harnessIO.bits.out.valid)),
-      ("A11", IOPin(harnessIO.bits.out.ready)),
-      ("D12", IOPin(harnessIO.bits.in.valid)),
-      ("D13", IOPin(harnessIO.bits.in.ready)),
-      ("B18", IOPin(harnessIO.bits.out.bits, 0)),
-      ("A18", IOPin(harnessIO.bits.out.bits, 1)),
-      ("K16", IOPin(harnessIO.bits.out.bits, 2)),
-      ("E15", IOPin(harnessIO.bits.out.bits, 3)),
-      ("E16", IOPin(harnessIO.bits.in.bits, 0)),
-      ("D15", IOPin(harnessIO.bits.in.bits, 1)),
-      ("C15", IOPin(harnessIO.bits.in.bits, 2)),
-      ("J17", IOPin(harnessIO.bits.in.bits, 3))
-    )
-    packagePinsWithPackageIOs foreach { case (pin, io) => {
-      artyTh.xdc.addPackagePin(io, pin)
-      artyTh.xdc.addIOStandard(io, "LVCMOS33")
-    }}
 
-    // Don't add IOB to the clock, if its an input
-    if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
-      packagePinsWithPackageIOs foreach { case (pin, io) => {
-        artyTh.xdc.addIOB(io)
-      }}
+    harnessIO match {
+      case io: DecoupledPhitIO => {
+        val clkIO = io match {
+          case io: InternalSyncPhitIO => IOPin(io.clock_out)
+          case io: ExternalSyncPhitIO => IOPin(io.clock_in)
+        }
+        val packagePinsWithPackageIOs = Seq(
+          ("G13", clkIO),
+          ("B11", IOPin(io.out.valid)),
+          ("A11", IOPin(io.out.ready)),
+          ("D12", IOPin(io.in.valid)),
+          ("D13", IOPin(io.in.ready)),
+          ("B18", IOPin(io.out.bits.phit, 0)),
+          ("A18", IOPin(io.out.bits.phit, 1)),
+          ("K16", IOPin(io.out.bits.phit, 2)),
+          ("E15", IOPin(io.out.bits.phit, 3)),
+          ("E16", IOPin(io.in.bits.phit, 0)),
+          ("D15", IOPin(io.in.bits.phit, 1)),
+          ("C15", IOPin(io.in.bits.phit, 2)),
+          ("J17", IOPin(io.in.bits.phit, 3))
+        )
+        packagePinsWithPackageIOs foreach { case (pin, io) => {
+          artyTh.xdc.addPackagePin(io, pin)
+          artyTh.xdc.addIOStandard(io, "LVCMOS33")
+        }}
+
+        // Don't add IOB to the clock, if its an input
+        io match {
+          case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
+            artyTh.xdc.addIOB(io)
+          }}
+          case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
+            artyTh.xdc.addIOB(io)
+          }}
+        }
+
+        artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
+        artyTh.sdc.addGroup(pins = Seq(clkIO))
+        artyTh.xdc.clockDedicatedRouteFalse(clkIO)
+      }
     }
-
-    artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
-    artyTh.sdc.addGroup(pins = Seq(clkIO))
-    artyTh.xdc.clockDedicatedRouteFalse(clkIO)
   }
 })
 
 // Maps the UART device to the on-board USB-UART
 class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTPort) => {
+  case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
     harnessIO <> port.io
@@ -114,7 +125,7 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
 class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
 
 class WithArty100TJTAG extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+  case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
     harnessIO <> port.io

fpga/src/main/scala/nexysvideo/Configs.scala

@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}
 
 // don't use FPGAShell's DesignKey
 class WithNoDesignKey extends Config((site, here, up) => {
-  case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+  case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })
 
 // DOC include start: WithNexysVideoTweaks and Rocket
@@ -60,6 +60,7 @@ class WithTinyNexysVideoTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(50.0) ++
   new chipyard.config.WithSystemBusFrequency(50.0) ++
   new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+  new chipyard.config.WithControlBusFrequency(50.0) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithNoDebug ++ // no jtag

fpga/src/main/scala/nexysvideo/Harness.scala

@@ -7,10 +7,10 @@ import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
 
 import sifive.blocks.devices.uart._
 

fpga/src/main/scala/nexysvideo/HarnessBinders.scala

@@ -15,7 +15,7 @@ import chipyard.harness._
 import chipyard.iobinders._
 
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
+  case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
     val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
     nexysvideoth.io_uart_bb.bundle <> port.io.uart
     nexysvideoth.other_leds(1) := port.io.dropped
@@ -27,7 +27,7 @@ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder
 })
 
 class WithNexysVideoDDRTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: TLMemPort) => {
+  case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
     val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
     val bundles = nexysTh.ddrClient.get.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))

fpga/src/main/scala/vc707/HarnessBinders.scala

@@ -16,21 +16,21 @@ import chipyard.iobinders._
 
 /*** UART ***/
 class WithVC707UARTHarnessBinder extends HarnessBinder({
-  case (th: VC707FPGATestHarnessImp, port: UARTPort) => {
+  case (th: VC707FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
     th.vc707Outer.io_uart_bb.bundle <> port.io
   }
 })
 
 /*** SPI ***/
 class WithVC707SPISDCardHarnessBinder extends HarnessBinder({
-  case (th: VC707FPGATestHarnessImp, port: SPIPort) => {
+  case (th: VC707FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
     th.vc707Outer.io_spi_bb.bundle <> port.io
   }
 })
 
 /*** Experimental DDR ***/
 class WithVC707DDRMemHarnessBinder extends HarnessBinder({
-  case (th: VC707FPGATestHarnessImp, port: TLMemPort) => {
+  case (th: VC707FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
     val bundles = th.vc707Outer.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }

fpga/src/main/scala/vc707/TestHarness.scala

@@ -7,11 +7,12 @@ import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem.{SystemBusKey}
 import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
+import freechips.rocketchip.prci._
 
 import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks.{PLLFactoryKey}
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
 
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
@@ -87,6 +88,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
 }
 
 class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+  override def provideImplicitClockToLazyChildren = true
   val vc707Outer = _outer
 
   val reset = IO(Input(Bool())).suggestName("reset")

fpga/src/main/scala/vcu118/Configs.scala

@@ -48,16 +48,17 @@ class WithVCU118Tweaks extends Config(
   new chipyard.config.WithSystemBusFrequency(100) ++
   new chipyard.config.WithControlBusFrequency(100) ++
   new chipyard.config.WithPeripheryBusFrequency(100) ++
+  new chipyard.config.WithControlBusFrequency(100) ++
   new WithFPGAFrequency(100) ++ // default 100MHz freq
   // harness binders
   new WithUART ++
   new WithSPISDCard ++
   new WithDDRMem ++
+  new WithJTAG ++
   // other configuration
   new WithDefaultPeripherals ++
   new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
   new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
-  new chipyard.config.WithNoDebug ++ // remove debug module
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
 )

fpga/src/main/scala/vcu118/CustomOverlays.scala

@@ -5,7 +5,7 @@ import chisel3._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell._
 import sifive.fpgashells.ip.xilinx._
 import sifive.fpgashells.shell.xilinx._
@@ -79,7 +79,7 @@ class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, va
     ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
     port.c0_sys_clk_i := sys.clock.asUInt
     port.sys_rst := sys.reset // pllReset
-    port.c0_ddr4_aresetn := !ar.reset
+    port.c0_ddr4_aresetn := !(ar.reset.asBool)
 
     // This was just copied from the SiFive example, but it's hard to follow.
     // The pins are emitted in the following order:

fpga/src/main/scala/vcu118/HarnessBinders.scala

@@ -15,24 +15,38 @@ import chipyard.iobinders._
 
 /*** UART ***/
 class WithUART extends HarnessBinder({
-  case (th: VCU118FPGATestHarnessImp, port: UARTPort) => {
+  case (th: VCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
     th.vcu118Outer.io_uart_bb.bundle <> port.io
   }
 })
 
 /*** SPI ***/
 class WithSPISDCard extends HarnessBinder({
-  case (th: VCU118FPGATestHarnessImp, port: SPIPort) => {
+  case (th: VCU118FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
     th.vcu118Outer.io_spi_bb.bundle <> port.io
   }
 })
 
 /*** Experimental DDR ***/
 class WithDDRMem extends HarnessBinder({
-  case (th: VCU118FPGATestHarnessImp, port: TLMemPort) => {
+  case (th: VCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
     val bundles = th.vcu118Outer.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
     ddrClientBundle <> port.io
   }
 })
+
+class WithJTAG extends HarnessBinder({
+  case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
+    val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
+    port.io.TCK := jtag_io.TCK
+    port.io.TMS := jtag_io.TMS
+    port.io.TDI := jtag_io.TDI
+    jtag_io.TDO.data := port.io.TDO
+    jtag_io.TDO.driven := true.B
+    // ignore srst_n
+    jtag_io.srst_n := DontCare
+
+  }
+})

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -8,11 +8,11 @@ import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
 import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
 
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
@@ -85,11 +85,15 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
   )))))
   ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
 
+  /*** JTAG ***/
+  val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())
+
   // module implementation
   override lazy val module = new VCU118FPGATestHarnessImp(this)
 }
 
 class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+  override def provideImplicitClockToLazyChildren = true
   val vcu118Outer = _outer
 
   val reset = IO(Input(Bool())).suggestName("reset")

fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala

@@ -1,28 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-
-import scala.collection.mutable.{LinkedHashMap}
-
-object BringupGPIOs {
-    // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?)
-    val pinMapping = LinkedHashMap(
-        // these connect to LEDs and switches on the VCU118 (and use 1.2V)
-        "led0"  -> ("AT32", "LVCMOS12", false), // 0
-        "led1"  -> ("AV34", "LVCMOS12", false), // 1
-        "led2"  -> ("AY30", "LVCMOS12", false), // 2
-        "led3"  -> ("BB32", "LVCMOS12", false), // 3
-        "led4"  -> ("BF32", "LVCMOS12", false), // 4
-        "led5"  -> ("AU37", "LVCMOS12", false), // 5
-        "led6"  -> ("AV36", "LVCMOS12", false), // 6
-        "led7"  -> ("BA37", "LVCMOS12", false), // 7
-        "sw0"   -> ("B17", "LVCMOS12", false), // 8
-        "sw1"   -> ("G16", "LVCMOS12", false), // 9
-        "sw2"   -> ("J16", "LVCMOS12", false), // 10
-        "sw3"   -> ("D21", "LVCMOS12", false) // 11
-    )
-
-    // return list of names (ordered)
-    def names: Seq[String] = pinMapping.keys.toSeq
-
-    // return number of GPIOs
-    def width: Int = pinMapping.size
-}

fpga/src/main/scala/vcu118/bringup/Configs.scala

@@ -1,97 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-
-import math.min
-
-import org.chipsalliance.cde.config.{Config, Parameters}
-import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.subsystem.{MasterPortParams}
-
-import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
-import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
-import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
-
-import sifive.fpgashells.shell.{DesignKey}
-import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
-
-import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
-
-import chipyard.{BuildSystem}
-
-import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size}
-import chipyard.iobinders.{WithGPIOPunchthrough}
-
-class WithBringupPeripherals extends Config((site, here, up) => {
-  case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
-  case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L)))
-  case PeripheryGPIOKey => {
-    if (BringupGPIOs.width > 0) {
-      require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
-      val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000))
-      val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32)
-      List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => {
-        GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport))
-      })
-    }
-    else {
-      List.empty[GPIOParams]
-    }
-  }
-  case TSIClockMaxFrequencyKey => 100
-  case PeripheryTSIHostKey => List(
-    TSIHostParams(
-      offchipSerialIfWidth = 4,
-      mmioBaseAddress = BigInt(0x64006000),
-      mmioSourceId = 1 << 13, // manager source
-      serdesParams = TSIHostSerdesParams(
-        clientPortParams = TLMasterPortParameters.v1(
-          clients = Seq(TLMasterParameters.v1(
-            name = "tl-tsi-host-serdes",
-            sourceId = IdRange(0, (1 << 13))))),
-        managerPortParams = TLSlavePortParameters.v1(
-          managers = Seq(TLSlaveParameters.v1(
-            address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip
-            regionType = RegionType.UNCACHED,
-            executable = true,
-            supportsGet        = TransferSizes(1, 64),
-            supportsPutFull    = TransferSizes(1, 64),
-            supportsPutPartial = TransferSizes(1, 64),
-            supportsAcquireT   = TransferSizes(1, 64),
-            supportsAcquireB   = TransferSizes(1, 64),
-            supportsArithmetic = TransferSizes(1, 64),
-            supportsLogical    = TransferSizes(1, 64))),
-          endSinkId = 1 << 6, // manager sink
-          beatBytes = 8)),
-      targetMasterPortParams = MasterPortParams(
-        base = BigInt("80000000", 16),
-        size = site(VCU118DDR2Size),
-        beatBytes = 8, // comes from test chip
-        idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG
-      ))
-})
-
-class WithBringupVCU118System extends Config((site, here, up) => {
-  case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top
-})
-
-class WithBringupAdditions extends Config(
-  new WithBringupUART ++
-  new WithBringupI2C ++
-  new WithBringupGPIO ++
-  new WithBringupTSIHost ++
-  new WithTSITLIOPassthrough ++
-  new WithGPIOPunchthrough ++
-  new WithBringupPeripherals ++
-  new WithBringupVCU118System)
-
-class RocketBringupConfig extends Config(
-  new WithBringupAdditions ++
-  new WithVCU118Tweaks ++
-  new chipyard.RocketConfig)
-
-class BoomBringupConfig extends Config(
-  new WithFPGAFrequency(50) ++
-  new WithBringupAdditions ++
-  new WithVCU118Tweaks ++
-  new chipyard.MegaBoomConfig)

fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala

@@ -1,204 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-
-import chisel3._
-import chisel3.experimental.{attach}
-
-import freechips.rocketchip.diplomacy._
-import org.chipsalliance.cde.config.{Parameters, Field}
-import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
-
-import sifive.fpgashells.shell._
-import sifive.fpgashells.ip.xilinx._
-import sifive.fpgashells.shell.xilinx._
-import sifive.fpgashells.clocks._
-import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
-
-import testchipip.tsi.{TSIHostWidgetIO}
-
-import chipyard.fpga.vcu118.{FMCPMap}
-
-/* Connect the I2C to certain FMC pins */
-class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput)
-  extends I2CXilinxPlacedOverlay(name, designInput, shellInput)
-{
-  shell { InModuleBody {
-    require(shellInput.index == 0) // only support 1 I2C <-> FMC connection
-    val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2")))
-    val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)),
-                                        (i2cLocations(shellInput.index)(1), IOPin(io.sda)))
-
-    packagePinsWithPackageIOs foreach { case (pin, io) => {
-      shell.xdc.addPackagePin(io, pin)
-      shell.xdc.addIOStandard(io, "LVCMOS18")
-      shell.xdc.addIOB(io)
-    } }
-  } }
-}
-
-class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName)
-  extends I2CShellPlacer[VCU118ShellBasicOverlays]
-{
-  def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
-}
-
-/* Connect the UART to certain FMC pins */
-class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput)
-  extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true)
-{
-  shell { InModuleBody {
-    val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused
-                                        (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused
-                                        (FMCPMap("C15"), IOPin(io.rxd)),
-                                        (FMCPMap("C14"), IOPin(io.txd)))
-
-    packagePinsWithPackageIOs foreach { case (pin, io) => {
-      shell.xdc.addPackagePin(io, pin)
-      shell.xdc.addIOStandard(io, "LVCMOS18")
-      shell.xdc.addIOB(io)
-    } }
-
-    // add pullup on ctsn (ctsn is an input that is not used or driven)
-    packagePinsWithPackageIOs take 1 foreach { case (pin, io) => {
-      shell.xdc.addPullup(io)
-    } }
-  } }
-}
-
-class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName)
-  extends UARTShellPlacer[VCU118ShellBasicOverlays] {
-  def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
-}
-
-/* Connect GPIOs to FPGA I/Os */
-abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput)
-  extends GPIOPlacedOverlay(name, di, si)
-{
-  def shell: XilinxShell
-
-  shell { InModuleBody {
-    (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) =>
-      val iobuf = Module(new IOBUF)
-      iobuf.suggestName(s"gpio_iobuf")
-      attach(ioPin, iobuf.io.IO)
-      sinkPin.i.ival := iobuf.io.O
-      iobuf.io.T := !sinkPin.o.oe
-      iobuf.io.I := sinkPin.o.oval
-    }
-  } }
-}
-
-class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String])
-   extends GPIOXilinxPlacedOverlay(name, designInput, shellInput)
-{
-  shell { InModuleBody {
-    require(gpioNames.length == io.gpio.length)
-
-    val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) =>
-      val (pin, iostd, pullupEnable) = BringupGPIOs.pinMapping(name)
-      (pin, iostd, pullupEnable, IOPin(io))
-    }
-
-    packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => {
-      shell.xdc.addPackagePin(io, pin)
-      shell.xdc.addIOStandard(io, iostd)
-      if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") }
-      if (pullupEnable) { shell.xdc.addPullup(io) }
-    } }
-  } }
-}
-
-class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName)
-  extends GPIOShellPlacer[VCU118ShellBasicOverlays] {
-  def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames)
-}
-
-case class TSIHostShellInput()
-case class TSIHostDesignInput(
-  serialIfWidth: Int,
-  node: BundleBridgeSource[TSIHostWidgetIO]
-  )(
-  implicit val p: Parameters)
-case class TSIHostOverlayOutput()
-trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
-
-case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil)
-
-abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput)
-  extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
-{
-  implicit val p = di.p
-}
-
-case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB
-class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput)
-  extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput)
-{
-  val tlTsiSerialSink = di.node.makeSink()
-  val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth))
-  val topTSIIONode = shell { tsiIoNode.makeSink() }
-
-  def overlayOutput = TSIHostOverlayOutput()
-  def ioFactory = new TSIHostWidgetIO(di.serialIfWidth)
-
-  InModuleBody {
-    // connect TSI serial
-    val tsiSourcePort = tsiIoNode.bundle
-    val tsiSinkPort = tlTsiSerialSink.bundle
-    tsiSinkPort.serial_clock := tsiSourcePort.serial_clock
-    tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits
-    tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid
-    tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready
-    tsiSinkPort.serial.in.bits  := tsiSourcePort.serial.in.bits
-    tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid
-    tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready
-  }
-}
-
-case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz
-class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput)
-  extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput)
-{
-  // connect the TSI port
-  shell { InModuleBody {
-    // connect TSI signals
-    val tsiPort = topTSIIONode.bundle
-    io <> tsiPort
-
-    require(di.serialIfWidth == 4)
-
-    val clkIo = IOPin(io.serial_clock)
-    val packagePinsWithPackageIOs = Seq(
-      (FMCPMap("D8"), clkIo),
-      (FMCPMap("D17"), IOPin(io.serial.out.ready)),
-      (FMCPMap("D18"), IOPin(io.serial.out.valid)),
-      (FMCPMap("D11"), IOPin(io.serial.out.bits, 0)),
-      (FMCPMap("D12"), IOPin(io.serial.out.bits, 1)),
-      (FMCPMap("D14"), IOPin(io.serial.out.bits, 2)),
-      (FMCPMap("D15"), IOPin(io.serial.out.bits, 3)),
-      (FMCPMap("D26"), IOPin(io.serial.in.ready)),
-      (FMCPMap("D27"), IOPin(io.serial.in.valid)),
-      (FMCPMap("D20"), IOPin(io.serial.in.bits, 0)),
-      (FMCPMap("D21"), IOPin(io.serial.in.bits, 1)),
-      (FMCPMap("D23"), IOPin(io.serial.in.bits, 2)),
-      (FMCPMap("D24"), IOPin(io.serial.in.bits, 3)))
-
-    packagePinsWithPackageIOs foreach { case (pin, io) => {
-      shell.xdc.addPackagePin(io, pin)
-      shell.xdc.addIOStandard(io, "LVCMOS18")
-    } }
-
-    // Don't add an IOB to the clock
-    (packagePinsWithPackageIOs take 1) foreach { case (pin, io) => {
-      shell.xdc.addIOB(io)
-    } }
-
-    shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey))
-    shell.sdc.addGroup(pins = Seq(clkIo))
-    shell.xdc.clockDedicatedRouteFalse(clkIo)
-  } }
-}
-
-class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName)
-  extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] {
-  def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
-}

fpga/src/main/scala/vcu118/bringup/DigitalTop.scala

@@ -1,26 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-
-import chisel3._
-
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.system._
-import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-
-import chipyard.{DigitalTop, DigitalTopModule}
-
-// ------------------------------------
-// Bringup VCU118 DigitalTop
-// ------------------------------------
-
-class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
-  with sifive.blocks.devices.i2c.HasPeripheryI2C
-  with testchipip.tsi.HasPeripheryTSIHostWidget
-{
-  override lazy val module = new BringupVCU118DigitalTopModule(this)
-}
-
-class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l)
-  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -1,51 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-
-import chisel3._
-import chisel3.experimental.{Analog, IO, BaseModule}
-
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.tilelink.{TLBundle}
-
-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
-import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
-import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
-import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
-
-import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
-
-import chipyard.harness._
-import chipyard.iobinders._
-
-/*** UART ***/
-class WithBringupUART extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort) => {
-    th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
-  }
-})
-
-/*** I2C ***/
-class WithBringupI2C extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort) => {
-    th.bringupOuter.io_i2c_bb.bundle <> port.io
-  }
-})
-
-/*** GPIO ***/
-class WithBringupGPIO extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort) => {
-    th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
-  }
-})
-
-/*** TSI Host Widget ***/
-class WithBringupTSIHost extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort) => {
-    val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
-    val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
-    tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    tsiDdrClientBundle <> port.io
-  }
-  case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort) => {
-    th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
-  }
-})

fpga/src/main/scala/vcu118/bringup/IOBinders.scala

@@ -1,30 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-
-import chisel3._
-import chisel3.experimental.{IO, DataMirror}
-
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.tilelink.{TLBundle}
-
-import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
-import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
-
-import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
-
-import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
-
-case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
-  extends Port[TSIHostWidgetIO]
-
-class WithTSITLIOPassthrough extends OverrideIOBinder({
-  (system: HasPeripheryTSIHostWidget) => {
-    require(system.tsiTLMem.size == 1)
-    val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave")
-    io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head
-
-    require(system.tsiSerial.size == 1)
-    val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
-    io_tsi_serial_pins_temp <> system.tsiSerial.head
-    (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
-  }
-})

fpga/src/main/scala/vcu118/bringup/TestHarness.scala

@@ -1,99 +0,0 @@
-package chipyard.fpga.vcu118.bringup
-import chisel3._
-
-import freechips.rocketchip.diplomacy._
-import org.chipsalliance.cde.config._
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tilelink._
-
-import sifive.fpgashells.shell.xilinx._
-import sifive.fpgashells.ip.xilinx._
-import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks._
-
-import sifive.blocks.devices.uart._
-import sifive.blocks.devices.spi._
-import sifive.blocks.devices.i2c._
-import sifive.blocks.devices.gpio._
-
-import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
-import testchipip.util.{TLSinkSetter}
-
-import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
-
-import chipyard.{ChipTop}
-import chipyard.harness._
-
-class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness {
-
-  /*** UART ***/
-
-  require(dp(PeripheryUARTKey).size == 2)
-
-  // 2nd UART goes to the FMC UART
-
-  val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
-
-  val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
-  dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb))
-
-  /*** I2C ***/
-
-  val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
-
-  val io_i2c_bb = BundleBridgeSource(() => (new I2CPort))
-  dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
-
-  /*** GPIO ***/
-
-  val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
-    val maxGPIOSupport = 32 // max gpio per gpio chip
-    val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
-    Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
-  })
-
-  val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
-  (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
-    placer.place(GPIODesignInput(params, io_gpio_bb(i)))
-  }
-
-  /*** TSI Host Widget ***/
-  require(dp(PeripheryTSIHostKey).size == 1)
-
-  // use the 2nd system clock for the 2nd DDR
-  val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node
-
-  val ddr2PLL = dp(PLLFactoryKey)()
-  ddr2PLL := sysClk2Node
-
-  val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
-  val ddr2Wrangler = LazyModule(new ResetWrangler)
-  val ddr2Group = ClockGroup()
-  ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL
-
-  val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
-
-  val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
-
-  val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth)))
-  dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))
-
-  // connect 1 mem. channel to the FPGA DDR
-  val tsiDdrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
-    name = "chip_ddr",
-    sourceId = IdRange(0, 64)
-  )))))
-  (ddr2Node
-    := TLFragmenter(8,64,holdFirstDeny=true)
-    := TLCacheCork()
-    := TLAtomicAutomata(passthrough=false)
-    := TLSinkSetter(64)
-    := tsiDdrClient)
-
-  // module implementation
-  override lazy val module = new BringupVCU118FPGATestHarnessImp(this)
-}
-
-class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) {
-  lazy val bringupOuter = _outer
-}

generators/chipyard/src/main/resources/csrc/spiketile.cc

@@ -12,7 +12,7 @@
 
 #if __has_include("spiketile_tsi.h")
 #define SPIKETILE_HTIF_TSI
-extern htif_t* tsi;
+extern std::map<int, htif_t*> tsis;
 #endif
 #if __has_include("spiketile_dtm.h")
 #define SPIKETILE_HTIF_DTM
@@ -346,8 +346,8 @@ extern "C" void spike_tile(int hartid, char* isa,
   chipyard_simif_t* simif = tile->simif;
   processor_t* proc = tile->proc;
 #if defined(SPIKETILE_HTIF_TSI)
-  if (!simif->htif && tsi)
-    simif->htif = tsi;
+  if (!simif->htif && tsis.size() > 0 && tsis[0])
+    simif->htif = tsis[0];
 #endif
 #if defined(SPIKETILE_HTIF_DTM)
   if (!simif->htif && dtm)

generators/chipyard/src/main/scala/ChipTop.scala

@@ -5,7 +5,6 @@ import chisel3._
 import scala.collection.mutable.{ArrayBuffer}
 
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
 import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
 import freechips.rocketchip.util.{DontTouch}

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -19,8 +19,11 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
   with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
+  with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
+  with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
   with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
+  with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
   with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
@@ -33,6 +36,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
   with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
+  with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
   with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
 {
@@ -40,13 +44,11 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
 }
 
 class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
-  with testchipip.cosim.CanHaveTraceIOModuleImp
   with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
   with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
   with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
   with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
   with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
-  with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop

generators/chipyard/src/main/scala/SpikeTile.scala

@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{IntParam, StringParam, IO}
+import chisel3.experimental.{IntParam, StringParam}
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
@@ -77,14 +77,15 @@ case class SpikeTileAttachParams(
 }
 
 case class SpikeTileParams(
-  hartId: Int = 0,
+  tileId: Int = 0,
   val core: SpikeCoreParams = SpikeCoreParams(),
   icacheParams: ICacheParams = ICacheParams(nWays = 32),
   dcacheParams: DCacheParams = DCacheParams(nWays = 32),
   tcmParams: Option[MasterPortParams] = None // tightly coupled memory
 ) extends InstantiableTileParams[SpikeTile]
 {
-  val name = Some("spike_tile")
+  val baseName = "spike_tile"
+  val uniqueName = s"${baseName}_$tileId"
   val beuAddr = None
   val blockerCtrlAddr = None
   val btb = None
@@ -92,7 +93,7 @@ case class SpikeTileParams(
   val dcache = Some(dcacheParams)
   val icache = Some(icacheParams)
   val clockSinkParams = ClockSinkParameters()
-  def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = {
+  def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = {
     new SpikeTile(this, crossing, lookup)
   }
 }
@@ -106,11 +107,11 @@ class SpikeTile(
     with SourcesExternalNotifications
 {
   // Private constructor ensures altered LazyModule.p is used implicitly
-  def this(params: SpikeTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+  def this(params: SpikeTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
     this(params, crossing.crossingType, lookup, p)
 
   // Required TileLink nodes
-  val intOutwardNode = IntIdentityNode()
+  val intOutwardNode = None
   val masterNode = visibilityNode
   val slaveNode = TLIdentityNode()
 
@@ -129,21 +130,21 @@ class SpikeTile(
   }
 
   ResourceBinding {
-    Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+    Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
   }
 
 
   val icacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
     sourceId = IdRange(0, 1),
-    name = s"Core ${staticIdForMetadataUseOnly} ICache")))))
+    name = s"Core ${tileId} ICache")))))
 
   val dcacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
-    name          = s"Core ${staticIdForMetadataUseOnly} DCache",
+    name          = s"Core ${tileId} DCache",
     sourceId      = IdRange(0, tileParams.dcache.get.nMSHRs),
     supportsProbe = TransferSizes(p(CacheBlockBytes), p(CacheBlockBytes)))))))
 
   val mmioNode = TLClientNode((Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
-    name          = s"Core ${staticIdForMetadataUseOnly} MMIO",
+    name          = s"Core ${tileId} MMIO",
     sourceId      = IdRange(0, 1),
     requestFifo   = true))))))
 
@@ -313,7 +314,7 @@ class SpikeBlackBox(
 }
 
 class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
-
+  val tileParams = outer.tileParams
   // We create a bundle here and decode the interrupt.
   val int_bundle = Wire(new TileInterrupts())
   outer.decodeCoreInterrupts(int_bundle)
@@ -337,7 +338,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   // then the DTM-based bringup with SimDTM will be used. This isn't required to be
   // true, but it usually is
   val useDTM = p(ExportDebug).protocols.contains(DMI)
-  val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs,
+  val spike = Module(new SpikeBlackBox(outer.tileId, outer.isaDTS, tileParams.core.nPMPs,
     tileParams.icache.get.nSets, tileParams.icache.get.nWays,
     tileParams.dcache.get.nSets, tileParams.dcache.get.nWays,
     tileParams.dcache.get.nMSHRs,
@@ -467,19 +468,21 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   }
 }
 
-class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(),
-  overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams()
+) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     // Calculate the next available hart ID (since hart ID cannot be duplicated)
     val prev = up(TilesLocated(InSubsystem), site)
-    val idOffset = overrideIdOffset.getOrElse(prev.size)
+    val idOffset = up(NumTiles)
     // Create TileAttachParams for every core to be instantiated
     (0 until n).map { i =>
       SpikeTileAttachParams(
-        tileParams = tileParams.copy(hartId = i + idOffset)
+        tileParams = tileParams.copy(tileId = i + idOffset)
       )
     } ++ prev
   }
+  case NumTiles => up(NumTiles) + n
+
 })
 
 class WithSpikeTCM extends Config((site, here, up) => {
@@ -492,5 +495,5 @@ class WithSpikeTCM extends Config((site, here, up) => {
     )))
   }
   case ExtMem => None
-  case BankedL2Key => up(BankedL2Key).copy(nBanks = 0)
+  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = 0)
 })

generators/chipyard/src/main/scala/Subsystem.scala

@@ -6,7 +6,6 @@
 package chipyard
 
 import chisel3._
-import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.prci._
 import org.chipsalliance.cde.config.{Field, Parameters}
@@ -71,18 +70,24 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
 }
 
 class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
-  with HasTiles
-  with HasPeripheryDebug
-  with CanHaveHTIF
-  with CanHaveChosenInDTS
+    with InstantiatesHierarchicalElements
+    with HasTileNotificationSinks
+    with HasTileInputConstants
+    with CanHavePeripheryCLINT
+    with CanHavePeripheryPLIC
+    with HasPeripheryDebug
+    with HasHierarchicalElementsRootContext
+    with HasHierarchicalElements
+    with CanHaveHTIF
+    with CanHaveChosenInDTS
 {
-  def coreMonitorBundles = tiles.map {
+  def coreMonitorBundles = totalTiles.values.map {
     case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
     case b: BoomTile => b.module.core.coreMonitorBundle
   }.toList
 
   // No-tile configs have to be handled specially.
-  if (tiles.size == 0) {
+  if (totalTiles.size == 0) {
     // no PLIC, so sink interrupts to nowhere
     require(!p(PLICKey).isDefined)
     val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head)
@@ -90,16 +95,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     intSink := intNexus :=* ibus.toPLIC
 
     // avoids a bug when there are no interrupt sources
-    ibus.fromAsync := NullIntSource()
+    ibus { ibus.fromAsync := NullIntSource() }
 
     // Need to have at least 1 driver to the tile notification sinks
     tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
     tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())
     tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple())
-
-    // Sink reset vectors to nowhere
-    val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W)))
-    resetVectorSink := tileResetVectorNode
   }
 
   // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
@@ -107,7 +108,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
   // ClockGroup. This makes it impossible to determine which clocks are driven
   // by which bus based on the member names, which is problematic when there is
   // a rational crossing between two buses. Instead, provide all bus clocks
-  // directly from the asyncClockGroupsNode in the subsystem to ensure bus
+  // directly from the allClockGroupsNode in the subsystem to ensure bus
   // names are always preserved in the top-level clock names.
   //
   // For example, using a RationalCrossing between the Sbus and Cbus, and
@@ -116,12 +117,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
   // Conversly, if an async crossing is used, they instead receive names of the
   // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases.
   Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>
-    tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }
+    tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := allClockGroupsNode }
   }
   override lazy val module = new ChipyardSubsystemModuleImp(this)
 }
 
 class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
-  with HasTilesModuleImp
+    with HasHierarchicalElementsRootContextModuleImp
 {
 }

generators/chipyard/src/main/scala/System.scala

@@ -32,13 +32,6 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
   val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
   val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
 
-  // If there is no bootrom, the tile reset vector bundle will be tied to zero
-  if (bootROM.isEmpty) {
-    val fakeResetVectorSourceNode = BundleBridgeSource[UInt]()
-    InModuleBody { fakeResetVectorSourceNode.bundle := 0.U }
-    tileResetVectorNexusNode := fakeResetVectorSourceNode
-  }
-
   override lazy val module = new ChipyardSystemModule(this)
 }
 

generators/chipyard/src/main/scala/TestSuites.scala

@@ -65,7 +65,7 @@ class TestSuiteHelper
   */
   def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
     val xlen = p(XLen)
-    tiles.find(_.hartId == 0).map { tileParams =>
+    tiles.find(_.tileId == 0).map { tileParams =>
       val coreParams = tileParams.core
       val vm = coreParams.useVM
       val env = if (vm) List("p","v") else List("p")

generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala

@@ -0,0 +1,27 @@
+package chipyard.clocking
+
+import chisel3._
+
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.prci._
+
+case object ClockTapKey extends Field[Boolean](true)
+
+trait CanHaveClockTap { this: BaseSubsystem =>
+  require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO")
+  val clockTapNode = Option.when(p(ClockTapKey)) {
+    val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
+    clockTap := ClockGroup() := allClockGroupsNode
+    clockTap
+  }
+  val clockTapIO = clockTapNode.map { node => InModuleBody {
+    val clock_tap = IO(Output(Clock()))
+    clock_tap := node.in.head._1.clock
+    clock_tap
+  }}
+}

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey, ClockPort, ResetPort}
+import chipyard.iobinders._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.subsystem._
@@ -14,31 +14,24 @@ import barstools.iocell.chisel._
 // blocks, which allow memory-mapped control of clock division, and clock muxing
 // between the FakePLL and the slow off-chip clock
 // Note: This will not simulate properly with firesim
-class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
+// Unsetting enable will prevent the divider/selector from actually modifying the clock,
+// while preserving the address map. Unsetting enable should only be done for RTL
+// simulators (Verilator) which do not model reset properly
+class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
   (system: HasChipyardPRCI) => {
     // Connect the implicit clock
     implicit val p = GetSystemParameters(system)
-    val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
-    system.connectImplicitClockSinkNode(implicitClockSinkNode)
-    InModuleBody {
-      val implicit_clock = implicitClockSinkNode.in.head._1.clock
-      val implicit_reset = implicitClockSinkNode.in.head._1.reset
-      system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
-        l.clock := implicit_clock
-        l.reset := implicit_reset
-      }}
-    }
     val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
     val baseAddress = system.prciParams.baseAddress
-    val clockDivider  = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
-    val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
+    val clockDivider  = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
+    val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
     val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
     clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
     clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
     pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
 
-    system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
+    system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 
     // Connect all other requested clocks
     val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
@@ -83,23 +76,12 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
 // This passes all clocks through to the TestHarness
 class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
   (system: HasChipyardPRCI) => {
-    // Connect the implicit clock
     implicit val p = GetSystemParameters(system)
-    val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
-    system.connectImplicitClockSinkNode(implicitClockSinkNode)
-    InModuleBody {
-      val implicit_clock = implicitClockSinkNode.in.head._1.clock
-      val implicit_reset = implicitClockSinkNode.in.head._1.reset
-      system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
-        l.clock := implicit_clock
-        l.reset := implicit_reset
-      }}
-    }
 
     // This aggregate node should do nothing
     val clockGroupAggNode = ClockGroupAggregateNode("fake")
     val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
-    system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
+    system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
 
     InModuleBody {
       val reset_io = IO(Input(AsyncReset()))
@@ -119,3 +101,12 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
     }
   }
 })
+
+class WithClockTapIOCells extends OverrideIOBinder({
+  (system: CanHaveClockTap) => {
+    system.clockTapIO.map { tap =>
+      val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
+      (Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
+    }.getOrElse((Nil, Nil))
+  }
+})

generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala

@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -30,15 +30,14 @@ case class ChipyardPRCIControlParams(
 
 case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
 
-trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
-  require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
+trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements =>
+  require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks")
 
   val prciParams = p(ChipyardPRCIControlKey)
 
   // Set up clock domain
   private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
-  val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
-  prci_ctrl_domain.clockNode := tlbus.fixedClockNode
+  val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
 
   val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
@@ -49,29 +48,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
 
   // Aggregate all the clock groups into a single node
   val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
-  val allClockGroupsNode = ClockGroupEphemeralNode()
 
-  // There are two "sets" of clocks which must be dealt with
-
-  // 1. The implicit clock from the subsystem. RC is moving away from depending on this
-  //    clock, but some modules still use it. Since the implicit clock sink node
-  //    is created in the ChipTop (the hierarchy wrapping the subsystem), this function
-  //    is provided to allow connecting that clock to the clock aggregator. This function
-  //    should be called in the ChipTop context
-  def connectImplicitClockSinkNode(sink: ClockSinkNode) = {
-    val implicitClockGrouper = this { ClockGroup() }
-    (sink
-      := implicitClockGrouper
-      := aggregator)
-  }
-
-  // 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode
+  // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode
   val clockNamePrefixer = ClockGroupNamePrefixer()
-  (asyncClockGroupsNode
+  (allClockGroupsNode
     :*= clockNamePrefixer
     :*= aggregator)
 
-
   // Once all the clocks are gathered in the aggregator node, several steps remain
   // 1. Assign frequencies to any clock groups which did not specify a frequency.
   // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain)
@@ -92,7 +75,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
   } }
   val tileResetSetter    = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
     val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
-      tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
+      tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
     reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
     reset_setter
   } }
@@ -116,11 +99,14 @@ RTL SIMULATORS, NAMELY VERILATOR.
 """ + Console.RESET)
   }
 
+  // The chiptopClockGroupsNode shouuld be what ClockBinders attach to
+  val chiptopClockGroupsNode = ClockGroupEphemeralNode()
+
   (aggregator
     := frequencySpecifier
     := clockGroupCombiner
     := resetSynchronizer
     := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
     := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
-    := allClockGroupsNode)
+    := chiptopClockGroupsNode)
 }

generators/chipyard/src/main/scala/clocking/TLClockDivider.scala

@@ -15,11 +15,27 @@ import testchipip.clocking._
 
 // This module adds a TileLink memory-mapped clock divider to the clock graph
 // The output clock/reset pairs from this module should be synchronized later
-class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule {
+// If enable is unset, this will not divide the clock
+// DO NOT unset enable for VLSI, or prototyping flows. The disable feature is a work around for
+// some RTL simulators which do not simulate the reset synchronization properly
+class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8, enable: Boolean = true)(implicit p: Parameters) extends LazyModule {
   val device = new SimpleDevice(s"clk-div-ctrl", Nil)
   val clockNode = ClockGroupIdentityNode()
   val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
 
+  if (!enable) println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+YOU ARE USING THE TLCLOCKDIVIDER IN
+"DISABLED" MODE. THIS SHOULD ONLY BE DONE
+FOR RTL SIMULATION
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+
   lazy val module = new LazyModuleImp(this) {
     require (clockNode.out.size == 1)
     val sources = clockNode.in.head._1.member.data.toSeq
@@ -45,13 +61,21 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
       // by setting divisor=0. The divisor signal into the ClockDividerOrPass is synchronized internally
       divider.io.divisor := Mux(busReset.asBool, 0.U, reg.io.q)
       divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
-      sinks(i)._2.clock := divider.io.clockOut
 
-      // Note this is not synchronized to the output clock, which takes time to appear
-      // so this is still asyncreset
-      // Stretch the reset for 40 cycles, to give enough time to reset any downstream
-      // digital logic
-      sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
+      if (enable) {
+        sinks(i)._2.clock := divider.io.clockOut
+
+        // Note this is not synchronized to the output clock, which takes time to appear
+        // so this is still asyncreset
+        // Stretch the reset for 40 cycles, to give enough time to reset any downstream
+        // digital logic
+        sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
+      } else {
+        // WARNING: THIS IS FOR RTL SIMULATION ONLY
+        sinks(i)._2.clock := sources(i).clock
+        sinks(i)._2.reset := sources(i).reset
+      }
+
       reg
     }
 

generators/chipyard/src/main/scala/clocking/TLClockSelector.scala

@@ -21,12 +21,30 @@ case class ClockSelNode()(implicit valName: ValName)
 
 // This module adds a TileLink memory-mapped clock mux for each downstream clock domain
 // in the clock graph. The output clock/reset should be synchronized downstream
-class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+// If enable is unset, this will always pass through the 0'th clock
+// DO NOT unset enable for VLSI, or prototyping flows. The disable feature is a work around for
+// some RTL simulators which do not simulate the reset synchronization properly
+class TLClockSelector(address: BigInt, beatBytes: Int, enable: Boolean = true)(implicit p: Parameters) extends LazyModule {
   val device = new SimpleDevice("clk-sel-ctrl", Nil)
   val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
 
   val clockNode = ClockSelNode()
 
+  if (!enable) println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+YOU ARE USING THE TLCLOCKSELECTOR IN
+"DISABLED" MODE. THIS SHOULD ONLY BE DONE
+FOR RTL SIMULATION
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+
+
+
   lazy val module = new LazyModuleImp(this) {
     val asyncReset = clockNode.in.map(_._1).map(_.reset).toSeq(0)
     val clocks = clockNode.in.map(_._1).map(_.clock)
@@ -43,10 +61,15 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
       val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
       mux.io.sel        := sel
       mux.io.resetAsync := asyncReset.asAsyncReset
-      sinks(i).clock := mux.io.clockOut
-      // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
-      sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
-
+      if (enable) {
+        sinks(i).clock := mux.io.clockOut
+        // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
+        sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
+      } else {
+        // WARNING: THIS IS FOR RTL SIMULATION ONLY
+        sinks(i).clock := clocks(0)
+        sinks(i).reset := asyncReset
+      }
       reg
     }
     tlNode.regmap((0 until sinks.size).map { i =>

generators/chipyard/src/main/scala/clocking/TileClockGater.scala

@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._

generators/chipyard/src/main/scala/clocking/TileResetSetter.scala

@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -11,23 +11,31 @@ import org.chipsalliance.cde.config.{Config}
 // --------------
 
 class AbstractConfig extends Config(
+  // ================================================
+  //   Set up TestHarness
+  // ================================================
   // The HarnessBinders control generation of hardware in the TestHarness
-  new chipyard.harness.WithUARTAdapter ++                          // add UART adapter to display UART on stdout, if uart is present
-  new chipyard.harness.WithBlackBoxSimMem ++                       // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
-  new chipyard.harness.WithSimTSIOverSerialTL ++                   // add external serial-adapter and RAM
-  new chipyard.harness.WithSimJTAGDebug ++                         // add SimJTAG if JTAG for debug exposed
-  new chipyard.harness.WithSimDMI ++                               // add SimJTAG if DMI exposed
-  new chipyard.harness.WithGPIOTiedOff ++                          // tie-off chiptop GPIOs, if GPIOs are present
-  new chipyard.harness.WithSimSPIFlashModel ++                     // add simulated SPI flash memory, if SPI is enabled
-  new chipyard.harness.WithSimAXIMMIO ++                           // add SimAXIMem for axi4 mmio port, if enabled
-  new chipyard.harness.WithTieOffInterrupts ++                     // tie-off interrupt ports, if present
-  new chipyard.harness.WithTieOffL2FBusAXI ++                      // tie-off external AXI4 master, if present
-  new chipyard.harness.WithCustomBootPinPlusArg ++                 // drive custom-boot pin with a plusarg, if custom-boot-pin is present
-  new chipyard.harness.WithSimUARTToUARTTSI ++                     // connect a SimUART to the UART-TSI port
-  new chipyard.harness.WithClockFromHarness ++                     // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
-  new chipyard.harness.WithResetFromHarness ++                     // reset controlled by harness
-  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
+  new chipyard.harness.WithUARTAdapter ++                          /** add UART adapter to display UART on stdout, if uart is present */
+  new chipyard.harness.WithBlackBoxSimMem ++                       /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */
+  new chipyard.harness.WithSimTSIOverSerialTL ++                   /** add external serial-adapter and RAM */
+  new chipyard.harness.WithSimJTAGDebug ++                         /** add SimJTAG if JTAG for debug exposed */
+  new chipyard.harness.WithSimDMI ++                               /** add SimJTAG if DMI exposed */
+  new chipyard.harness.WithGPIOTiedOff ++                          /** tie-off chiptop GPIOs, if GPIOs are present */
+  new chipyard.harness.WithSimSPIFlashModel ++                     /** add simulated SPI flash memory, if SPI is enabled */
+  new chipyard.harness.WithSimAXIMMIO ++                           /** add SimAXIMem for axi4 mmio port, if enabled */
+  new chipyard.harness.WithTieOffInterrupts ++                     /** tie-off interrupt ports, if present */
+  new chipyard.harness.WithTieOffL2FBusAXI ++                      /** tie-off external AXI4 master, if present */
+  new chipyard.harness.WithCustomBootPinPlusArg ++                 /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
+  new chipyard.harness.WithDriveChipIdPin ++                       /** drive chip id pin from harness binder, if chip id pin is present */
+  new chipyard.harness.WithSimUARTToUARTTSI ++                     /** connect a SimUART to the UART-TSI port */
+  new chipyard.harness.WithClockFromHarness ++                     /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
+  new chipyard.harness.WithResetFromHarness ++                     /** reset controlled by harness */
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
 
+
+  // ================================================
+  //   Set up I/O cells + punch I/Os in ChipTop
+  // ================================================
   // The IOBinders instantiate ChipTop IOs to match desired digital IOs
   // IOCells are generated for "Chip-like" IOs
   new chipyard.iobinders.WithSerialTLIOCells ++
@@ -36,6 +44,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithGPIOCells ++
   new chipyard.iobinders.WithSPIFlashIOCells ++
   new chipyard.iobinders.WithExtInterruptIOCells ++
+  new chipyard.iobinders.WithChipIdIOCells ++
   new chipyard.iobinders.WithCustomBootPin ++
   // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO
   // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop
@@ -51,40 +60,98 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
 
-  // By default, punch out IOs to the Harness
-  new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
-  new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
-  new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
-  new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus
-  new chipyard.config.WithSystemBusFrequency(500.0) ++              // Default 500 MHz sbus
-  new chipyard.config.WithFrontBusFrequency(500.0) ++               // Default 500 MHz fbus
-  new chipyard.config.WithOffchipBusFrequency(500.0) ++             // Default 500 MHz obus
 
-  new testchipip.boot.WithCustomBootPin ++                          // add a custom-boot-pin to support pin-driven boot address
-  new testchipip.boot.WithBootAddrReg ++                            // add a boot-addr-reg for configurable boot address
-  new testchipip.serdes.WithSerialTL(Seq(                           // add a serial-tilelink interface
+  // ================================================
+  //   Set up External Memory and IO Devices
+  // ================================================
+  // External memory section
+  new testchipip.serdes.WithSerialTL(Seq(                           /** add a serial-tilelink interface */
     testchipip.serdes.SerialTLParams(
-      client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
-      width = 32                                                    // serial-tilelink interface with 32 lanes
+      client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
     )
   )) ++
-  new testchipip.soc.WithMbusScratchpad(base = 0x08000000,          // add 64 KiB on-chip scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++         /** Default 1 AXI-4 memory channels */
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++                 /** no top-level MMIO master port (overrides default set in rocketchip) */
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++                /** no top-level MMIO slave port (overrides default set in rocketchip) */
+
+  // MMIO device section
+  new chipyard.config.WithUART ++                                  /** add a UART */
+
+
+  // ================================================
+  //   Set up Debug/Bringup/Testing Features
+  // ================================================
+  // JTAG
+  new freechips.rocketchip.subsystem.WithDebugSBA ++                /** enable the SBA (system-bus-access) feature of the debug module */
+  new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        /** increase debug module data word capacity */
+  new freechips.rocketchip.subsystem.WithJtagDTM ++                 /** set the debug module to expose a JTAG port */
+
+  // Boot Select Pins
+  new testchipip.boot.WithCustomBootPin ++                          /** add a custom-boot-pin to support pin-driven boot address */
+  new testchipip.boot.WithBootAddrReg ++                            /** add a boot-addr-reg for configurable boot address */
+
+
+  // ================================================
+  //   Set up Interrupts
+  // ================================================
+  // CLINT and PLIC related settings goes here
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++    /** no external interrupts */
+
+
+  // ================================================
+  //   Set up Tiles
+  // ================================================
+  // tile-local settings goes here
+
+
+  // ================================================
+  //   Set up Memory system
+  // ================================================
+  // On-chip memory section
+  new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */
+  new chipyard.config.WithBootROM ++                                     /** use default bootrom */
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000,               /** add 64 KiB on-chip scratchpad */
                                         size = 64 * 1024) ++
-  new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
-  new chipyard.config.WithBootROM ++                                // use default bootrom
-  new chipyard.config.WithUART ++                                   // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
-  new chipyard.config.WithNoSubsystemDrivenClocks ++                // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
-  new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++      // Default 1 memory channels
-  new freechips.rocketchip.subsystem.WithClockGateModel ++          // add default EICG_wrapper clock gate model
-  new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++              // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++             // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++          // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++    // no external interrupts
-  new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
-  new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
-  new freechips.rocketchip.system.BaseConfig)                       // "base" rocketchip system
+
+  // Coherency settings
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++          /** use Sifive LLC cache as root of coherence */
+
+  // Bus/interconnect settings
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
+
+
+  // ================================================
+  //   Set up power, reset and clocking
+  // ================================================
+
+  // ChipTop clock IO/PLL/Divider/Mux settings
+  new chipyard.clocking.WithClockTapIOCells ++                      /** Default generate a clock tapio */
+  new chipyard.clocking.WithPassthroughClockGenerator ++
+
+  // DigitalTop-internal clocking settings
+  new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++  /** leave the bus clocks undriven by sbus */
+  new freechips.rocketchip.subsystem.WithClockGateModel ++              /** add default EICG_wrapper clock gate model */
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore",        /** create a "uncore" clock group tieing all the bus clocks together */
+    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), 
+    Seq("tile"))) ++
+
+  new chipyard.config.WithPeripheryBusFrequency(500.0) ++           /** Default 500 MHz pbus */
+  new chipyard.config.WithMemoryBusFrequency(500.0) ++              /** Default 500 MHz mbus */
+  new chipyard.config.WithControlBusFrequency(500.0) ++             /** Default 500 MHz cbus */
+  new chipyard.config.WithSystemBusFrequency(500.0) ++              /** Default 500 MHz sbus */
+  new chipyard.config.WithFrontBusFrequency(500.0) ++               /** Default 500 MHz fbus */
+  new chipyard.config.WithOffchipBusFrequency(500.0) ++             /** Default 500 MHz obus */
+  new chipyard.config.WithInheritBusFrequencyAssignments ++         /** Unspecified clocks within a bus will receive the bus frequency if set */
+  new chipyard.config.WithNoSubsystemClockIO ++                     /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
+
+  // reset
+
+  // power
+
+
+  // ==================================
+  //   Base Settings
+  // ==================================
+  new freechips.rocketchip.system.BaseConfig                        /** "base" rocketchip system */
+)

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -22,8 +22,18 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up I/O
   //==================================
-  new testchipip.serdes.WithSerialTLWidth(4) ++                                         // 4bit wide Serialized TL interface to minimize IO
-  new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++                       // Configure the off-chip memory accessible over serial-tl as backing memory
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(              // 1 serial tilelink port
+    manager = Some(testchipip.serdes.SerialTLManagerParams(                             // port acts as a manager of offchip memory
+      memParams = Seq(testchipip.serdes.ManagerRAMParams(                               // 4 GB of off-chip memory
+        address = BigInt("80000000", 16),
+        size    = BigInt("100000000", 16)
+      )),
+      isMemoryDevice = true
+    )),
+    client = Some(testchipip.serdes.SerialTLClientParams()),                            // Allow an external manager to probe this chip
+    phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16)   // 4-bit bidir interface, sync'd to an external clock
+  ))) ++
+
   new freechips.rocketchip.subsystem.WithNoMemPort ++                                   // Remove axi4 mem port
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel
 
@@ -60,10 +70,16 @@ class ChipBringupHostConfig extends Config(
   //=============================
   // Setup the SerialTL side on the bringup device
   //=============================
-  new testchipip.serdes.WithSerialTLWidth(4) ++                                // match width with the chip
-  new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L,        // accessible memory of the chip that doesn't come from the tethered host
-                                        idBits = 4, isMainMemory = false) ++   // This assumes off-chip mem starts at 0x8000_0000
-  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
+    manager = Some(testchipip.serdes.SerialTLManagerParams(
+      memParams = Seq(testchipip.serdes.ManagerRAMParams(                            // Bringup platform can access all memory from 0 to DRAM_BASE
+        address = BigInt("00000000", 16),
+        size    = BigInt("80000000", 16)
+      ))
+    )),
+    client = Some(testchipip.serdes.SerialTLClientParams()),                                        // Allow chip to access this device's memory (DRAM)
+    phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
+  ))) ++
 
   //============================
   // Setup bus topology on the bringup system
@@ -110,5 +126,9 @@ class TetheredChipLikeRocketConfig extends Config(
 class VerilatorCITetheredChipLikeRocketConfig extends Config(
   new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++   // use absolute freqs for sims in the harness
   new chipyard.harness.WithMultiChipSerialTL(0, 1) ++                // connect the serial-tl ports of the chips together
-  new chipyard.harness.WithMultiChip(0, new chipyard.config.WithNoResetSynchronizers ++ new ChipLikeRocketConfig) ++
+  new chipyard.harness.WithMultiChip(0,                                         // These fragments remove all troublesome
+    new chipyard.clocking.WithPLLSelectorDividerClockGenerator(enable=false) ++ // clocking features from the design
+    new chipyard.iobinders.WithDebugIOCells(syncReset = false) ++
+    new chipyard.config.WithNoResetSynchronizers ++
+    new ChipLikeRocketConfig) ++
   new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))

generators/chipyard/src/main/scala/config/ChipletConfigs.scala

@@ -0,0 +1,93 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.subsystem.{SBUS}
+import testchipip.soc.{OBUS}
+
+// ------------------------------------------------
+// Configs demonstrating chip-to-chip communication
+// ------------------------------------------------
+
+// Simple design which exposes a second serial-tl port that can connect to another instance of itself
+class SymmetricChipletRocketConfig extends Config(
+  new testchipip.soc.WithChipIdPin ++                               // Add pin to identify chips
+  new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(                               // 0th serial-tl is chip-to-bringup-fpga
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // bringup serial-tl acts only as a client
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams()   // bringup serial-tl is sync'd to external clock
+    ),
+    testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // chip-to-chip serial-tl acts as a client
+      manager = Some(testchipip.serdes.SerialTLManagerParams(       // chip-to-chip serial-tl managers other chip's memory
+        memParams = Seq(testchipip.serdes.ManagerRAMParams(
+          address = 0,
+          size = 1L << 32,
+        )),
+        slaveWhere = OBUS
+      )),
+      phyParams = testchipip.serdes.SourceSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+    ))
+  ) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS,                     // obus provides path to other chip's memory
+    blockRange = Seq(AddressSet(0, (1L << 32) - 1)),                // The lower 4GB is mapped to this chip
+    replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
+  ) ++
+  new testchipip.soc.WithOffchipBus ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
+class MultiSimSymmetricChipletRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=1) ++
+  new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
+  new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
+)
+
+// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet
+class RocketCoreChipletConfig extends Config(
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(
+      client = Some(testchipip.serdes.SerialTLClientParams()),
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+    ),
+    testchipip.serdes.SerialTLParams(
+      manager = Some(testchipip.serdes.SerialTLManagerParams(
+        cohParams = Seq(testchipip.serdes.ManagerCOHParams(
+          address = BigInt("80000000", 16),
+          size    = BigInt("100000000", 16)
+        )),
+        slaveWhere = OBUS,
+        isMemoryDevice = true
+      )),
+      phyParams = testchipip.serdes.SourceSyncSerialPhyParams()
+    )
+  )) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS) ++
+  new testchipip.soc.WithOffchipBus ++
+  new testchipip.soc.WithNoScratchpads ++
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// LLC-only chiplet
+class LLCChipletConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
+    client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)),
+    phyParams = testchipip.serdes.SourceSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+  ))) ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
+  new chipyard.NoCoresConfig
+)
+
+class MultiSimLLCChipletRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++
+  new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++
+  new chipyard.harness.WithMultiChip(1, new LLCChipletConfig)
+)

generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

@@ -39,3 +39,8 @@ class QuadChannelRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
+
+class BroadcastCoherenceRocketConfig extends Config(
+  new chipyard.config.WithBroadcastManager ++                 // Use broadcast-based coherence hub
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -75,6 +75,7 @@ class ManyPeripheralsRocketConfig extends Config(
   new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
   new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+  new chipyard.config.WithPeripheryTimer ++                  // add the pwm timer device
   new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -2,6 +2,7 @@ package chipyard
 
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.subsystem.{InCluster}
 
 // --------------
 // Rocket Configs
@@ -62,7 +63,7 @@ class MulticlockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   // Frequency specifications
   new chipyard.config.WithTileFrequency(1000.0) ++        // Matches the maximum frequency of U540
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore"   , Seq("sbus", "cbus", "implicit"), Nil),
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore"   , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil),
                                                       ("periphery", Seq("pbus", "fbus"), Nil)) ++
   new chipyard.config.WithSystemBusFrequency(500.0) ++    // Matches the maximum frequency of U540
   new chipyard.config.WithMemoryBusFrequency(500.0) ++    // Matches the maximum frequency of U540
@@ -88,3 +89,14 @@ class PrefetchingRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++                           // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                               // single rocket-core
   new chipyard.config.AbstractConfig)
+
+class ClusteredRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(1)) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(0)) ++
+  new freechips.rocketchip.subsystem.WithCluster(1) ++
+  new freechips.rocketchip.subsystem.WithCluster(0) ++
+  new chipyard.config.AbstractConfig)
+
+class FastRTLSimRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+  new chipyard.RocketConfig)

generators/chipyard/src/main/scala/config/TracegenConfigs.scala

@@ -12,10 +12,11 @@ class AbstractTraceGenConfig extends Config(
   new chipyard.iobinders.WithAXI4MemPunchthrough ++
   new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
   new chipyard.config.WithTracegenSystem ++
-  new chipyard.config.WithNoSubsystemDrivenClocks ++
+  new chipyard.config.WithNoSubsystemClockIO ++
   new chipyard.config.WithMemoryBusFrequency(1000.0) ++
+  new chipyard.config.WithControlBusFrequency(1000.0) ++
   new chipyard.config.WithSystemBusFrequency(1000.0) ++
   new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++

generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala

@@ -19,8 +19,8 @@ import testchipip.soc.{OffchipBusKey}
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
 // the diplomacy graph upwards into the ChipTop, where we connect it to
 // our clock drivers
-class WithNoSubsystemDrivenClocks extends Config((site, here, up) => {
-  case SubsystemDriveAsyncClockGroupsKey => None
+class WithNoSubsystemClockIO extends Config((site, here, up) => {
+  case SubsystemDriveClockGroupsFromIO => false
 })
 
 /**
@@ -111,14 +111,22 @@ class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) =
 class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
 class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
 
+// Remove the tile clock gaters in this system
 class WithNoTileClockGaters extends Config((site, here, up) => {
   case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileClockGating = false)
 })
 
+// Remove the tile reset control blocks in this system
 class WithNoTileResetSetters extends Config((site, here, up) => {
   case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileResetSetting = false)
 })
 
+// Remove the global reset synchronizers in this system
 class WithNoResetSynchronizers extends Config((site, here, up) => {
   case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
 })
+
+// Remove any ClockTap ports in this system
+class WithNoClockTap extends Config((site, here, up) => {
+  case ClockTapKey => false
+})

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -16,6 +16,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.i2c._
+import sifive.blocks.devices.timer._
 
 import testchipip._
 
@@ -169,3 +170,7 @@ class WithNoBusErrorDevices extends Config((site, here, up) => {
   case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None)
   case FrontBusKey => up(FrontBusKey).copy(errorDevice = None)
 })
+
+class WithPeripheryTimer(timerParams: TimerParams = TimerParams(0x4000)) extends Config((site, here, up) => {
+  case PeripheryTimerKey => Seq(timerParams)
+})

generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala

@@ -12,15 +12,15 @@ import gemmini._
 import chipyard.{TestSuitesKey, TestSuiteHelper}
 
 /**
- * Map from a hartId to a particular RoCC accelerator
+ * Map from a tileId to a particular RoCC accelerator
  */
 case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
 
 /**
- * Config fragment to enable different RoCCs based on the hartId
+ * Config fragment to enable different RoCCs based on the tileId
  */
 class WithMultiRoCC extends Config((site, here, up) => {
-  case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
+  case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).tileId, Nil)
 })
 
 /**
@@ -39,7 +39,7 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
  *
  * For ex:
  *   Core 0, 1, 2, 3 have been defined earlier
- *     with hartIds of 0, 1, 2, 3 respectively
+ *     with tileIds of 0, 1, 2, 3 respectively
  *   And you call WithMultiRoCCHwacha(0,1)
  *   Then Core 0 and 1 will get a Hwacha
  *

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -7,7 +7,7 @@ import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence
 class WithBroadcastManager extends Config((site, here, up) => {
-  case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
+  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
 })
 
 class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => {

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -78,7 +78,7 @@ class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up)
 class WithRocketICacheScratchpad extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.hartId * 0x10000)))
+      icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.tileId * 0x10000)))
     ))
   }
 })
@@ -86,7 +86,7 @@ class WithRocketICacheScratchpad extends Config((site, here, up) => {
 class WithRocketDCacheScratchpad extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.hartId * 0x10000)))
+      dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.tileId * 0x10000)))
     ))
   }
 })
@@ -94,15 +94,15 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
 class WithTilePrefetchers extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
     case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
     case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
     case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
     case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
   }
 })
 

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -30,9 +30,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
   //========================
   // Diplomatic clock stuff
   //========================
-  val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
-  system.connectImplicitClockSinkNode(implicitClockSinkNode)
-
   val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere)
   val baseAddress = system.prciParams.baseAddress
   val clockDivider  = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
@@ -43,7 +40,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
   tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
   tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
 
-  system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
+  system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 
   // Connect all other requested clocks
   val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
@@ -69,13 +66,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
     //=========================
     // Clock/reset
     //=========================
-    val implicit_clock = implicitClockSinkNode.in.head._1.clock
-    val implicit_reset = implicitClockSinkNode.in.head._1.reset
-    system.module match { case l: LazyModuleImp => {
-      l.clock := implicit_clock
-      l.reset := implicit_reset
-    }}
-
     val clock_wire = Wire(Input(Clock()))
     val reset_wire = Wire(Input(AsyncReset()))
     val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -1,7 +1,6 @@
 package chipyard.example
 
 import chisel3._
-import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 
 import org.chipsalliance.cde.config.{Field, Parameters}
@@ -11,10 +10,10 @@ import freechips.rocketchip.util.{PlusArg}
 import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.serdes.{SerialTLKey}
+import testchipip.serdes._
 import testchipip.uart.{UARTAdapter}
 import testchipip.dram.{SimDRAM}
-import testchipip.tsi.{TSIHarness, SimTSI}
+import testchipip.tsi.{TSIHarness, SimTSI, SerialRAM}
 import chipyard.harness.{BuildTop}
 
 // A "flat" TestHarness that doesn't use IOBinders
@@ -46,18 +45,28 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
   val serialTLManagerParams = sVal.manager.get
   require(serialTLManagerParams.isMemoryDevice)
 
-  withClockAndReset(clock, reset) {
-    val serial_bits = dut.serial_tl_pad.bits
-    if (DataMirror.directionOf(dut.serial_tl_pad.clock) == Direction.Input) {
-      dut.serial_tl_pad.clock := clock
-    }
-    val harnessRAM = TSIHarness.connectRAM(
-      p(SerialTLKey)(0),
-      lazyDut.system.serdessers(0),
-      serial_bits,
-      reset)
-    io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset)
+  // Figure out which clock drives the harness TLSerdes, based on the port type
+  val serial_ram_clock = dut.serial_tl_pad match {
+    case io: InternalSyncPhitIO => io.clock_out
+    case io: ExternalSyncPhitIO => clock
+  }
+  dut.serial_tl_pad match {
+    case io: ExternalSyncPhitIO => io.clock_in := clock
+    case io: InternalSyncPhitIO =>
+  }
 
+  dut.serial_tl_pad match {
+    case pad: DecoupledPhitIO => {
+      withClockAndReset(serial_ram_clock, reset) {
+        // SerialRAM implements the memory regions the chip expects
+        val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)
+        ram.io.ser.in <> pad.out
+        pad.in <> ram.io.ser.out
+
+        // Allow TSI to master the chip
+        io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset)
+      }
+    }
   }
 
   // JTAG