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[skip ci] address comments, instantiate Sha3Accel module

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Harrison Liew
2019-09-27 09:37:27 -07:00
parent 8fffc1c670
commit 35566195db
3 changed files with 28 additions and 120 deletions
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docs/VLSI/Advanced-Usage.rst
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@@ -5,14 +5,14 @@ Advanced Usage
Alternative RTL Flows
---------------------
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to give the following environment variables ``make buildfile`` (or edit them directly in the Makefile).
.. code-block:: shell
export CUSTOM_VLOG=<your verilog files>
export VLSI_TOP=<your top module>
CUSTOM_VLOG=<your verilog files>
VLSI_TOP=<your top module>
``CUSTOM_VLOG`` breaks the dependency on the rest of the
``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files.
Under the Hood
--------------