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Rename useVxCache

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This commit is contained in:
Hansung Kim
2023-10-13 14:23:24 -07:00
parent 304ea362d0
commit 355fedd79d
1 changed files with 3 additions and 2 deletions
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5
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -36,20 +36,21 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
})
class RadianceConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(use_vx_cache = false) ++
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
// new freechips.rocketchip.subsystem.WithNoMemPort ++
// new testchipip.WithSbusScratchpad(banks=2) ++
// new testchipip.WithMbusScratchpad(banks=2) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
// new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/vcs/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/vcs/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/vcs/op_b.bin") ++
new AbstractConfig)
class RadianceConfigVortexCache extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(use_vx_cache = true) ++
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = true) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
// new freechips.rocketchip.subsystem.WithNoMemPort ++
// new testchipip.WithSbusScratchpad(banks=2) ++