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Merge branch 'main' into install-circt-out-of-conda

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This commit is contained in:
Abraham Gonzalez
2023-12-07 11:10:44 -08:00
committed by GitHub
parent 551c096bc9 a149085a90
commit 3df5e62602
7 changed files with 23 additions and 23 deletions
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4
.github/scripts/defaults.sh vendored
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@@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya
grouping["group-constellation"]="chipyard-constellation" grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118" grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
# key value store to get the build strings # key value store to get the build strings
declare -A mapping declare -A mapping
@@ -79,7 +79,7 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo
mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig" mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig" mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"
mapping["arty"]="SUB_PROJECT=arty verilog" mapping["arty35t"]="SUB_PROJECT=arty35t verilog"
mapping["arty100t"]="SUB_PROJECT=arty100t verilog" mapping["arty100t"]="SUB_PROJECT=arty100t verilog"
mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog" mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog"
mapping["vc707"]="SUB_PROJECT=vc707 verilog" mapping["vc707"]="SUB_PROJECT=vc707 verilog"

6
fpga/Makefile
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@@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
FPGA_BRAND ?= xilinx FPGA_BRAND ?= xilinx
endif endif
ifeq ($(SUB_PROJECT),arty) ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty # TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= fpga_platforms
MODEL ?= ArtyFPGATestHarness MODEL ?= Arty35THarness
VLOG_MODEL ?= ArtyFPGATestHarness VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty CONFIG_PACKAGE ?= chipyard.fpga.arty

8
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
import chipyard.iobinders._ import chipyard.iobinders._
class WithArtyDebugResetHarnessBinder extends HarnessBinder({ class WithArtyDebugResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: DebugResetPort) => { case (th: Arty35THarness, port: DebugResetPort) => {
th.dut_ndreset := port.io // Debug module reset th.dut_ndreset := port.io // Debug module reset
} }
}) })
class WithArtyJTAGResetHarnessBinder extends HarnessBinder({ class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGResetPort) => { case (th: Arty35THarness, port: JTAGResetPort) => {
port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
} }
}) })
class WithArtyJTAGHarnessBinder extends HarnessBinder({ class WithArtyJTAGHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGPort) => { case (th: Arty35THarness, port: JTAGPort) => {
val jtag_wire = Wire(new JTAGIO) val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := port.io.TDO jtag_wire.TDO.data := port.io.TDO
jtag_wire.TDO.driven := true.B jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
}) })
class WithArtyUARTHarnessBinder extends HarnessBinder({ class WithArtyUARTHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: UARTPort) => { case (th: Arty35THarness, port: UARTPort) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) { withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_rxd_out, port.io.txd) IOBUF(th.uart_rxd_out, port.io.txd)
port.io.rxd := IOBUF(th.uart_txd_in) port.io.rxd := IOBUF(th.uart_txd_in)

2
fpga/src/main/scala/arty/TestHarness.scala
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@@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{HasHarnessInstantiators} import chipyard.harness.{HasHarnessInstantiators}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators { class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type. // Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset()) val hReset = Wire(Reset())
hReset := ~ck_rst hReset := ~ck_rst

20
generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
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@@ -24,42 +24,42 @@ object ApplyMultiHarnessBinders {
Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) { Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) {
(chips(i), chips(j)) match { (chips(i), chips(j)) match {
case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f => case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f =>
f(l0.ports, l1.ports) f(th, l0.ports, l1.ports)
} }
} }
}} }}
} }
} }
class MultiHarnessBinder[T <: Port[_]]( class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators](
chip0: Int, chip1: Int, chip0: Int, chip1: Int,
chip0portFn: T => Boolean, chip1portFn: T => Boolean, chip0portFn: T => Boolean, chip1portFn: T => Boolean,
connectFn: (T, T) => Unit connectFn: (S, T, T) => Unit
)(implicit tag: ClassTag[T]) extends Config((site, here, up) => { )(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => {
// Override any HarnessBinders for chip0/chip1 // Override any HarnessBinders for chip0/chip1
case MultiChipParameters(`chip0`) => new Config( case MultiChipParameters(`chip0`) => new Config(
new HarnessBinder({case (th, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0)) new HarnessBinder({case (th: S, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
) )
case MultiChipParameters(`chip1`) => new Config( case MultiChipParameters(`chip1`) => new Config(
new HarnessBinder({case (th, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1)) new HarnessBinder({case (th: S, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
) )
// Set the multiharnessbinder key // Set the multiharnessbinder key
case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ { case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ {
((chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => { ((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p } val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p }
val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p } val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p }
require(chip0Port.size == 1 && chip1Port.size == 1) require(chip0Port.size == 1 && chip1Port.size == 1)
connectFn(chip0Port(0), chip1Port(0)) connectFn(th, chip0Port(0), chip1Port(0))
}) })
} }
}) })
class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder[SerialTLPort]( class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder(
chip0, chip1, chip0, chip1,
(p0: SerialTLPort) => p0.portId == chip0portId, (p0: SerialTLPort) => p0.portId == chip0portId,
(p1: SerialTLPort) => p1.portId == chip1portId, (p1: SerialTLPort) => p1.portId == chip1portId,
(p0: SerialTLPort, p1: SerialTLPort) => { (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
(DataMirror.directionOf(p0.io.clock), DataMirror.directionOf(p1.io.clock)) match { (DataMirror.directionOf(p0.io.clock), DataMirror.directionOf(p1.io.clock)) match {
case (Direction.Input, Direction.Output) => p0.io.clock := p1.io.clock case (Direction.Input, Direction.Output) => p0.io.clock := p1.io.clock
case (Direction.Output, Direction.Input) => p1.io.clock := p0.io.clock case (Direction.Output, Direction.Input) => p1.io.clock := p0.io.clock

2
generators/chipyard/src/main/scala/harness/package.scala
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@@ -7,5 +7,5 @@ package object harness
{ {
import chipyard.iobinders.Port import chipyard.iobinders.Port
type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit] type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit]
type MultiHarnessBinderFunction = (Seq[Port[_]], Seq[Port[_]]) => Unit type MultiHarnessBinderFunction = (HasHarnessInstantiators, Seq[Port[_]], Seq[Port[_]]) => Unit
} }

4
tests/blkdev.c
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@@ -59,8 +59,8 @@ void blkdev_write(unsigned long offset, void *addr, size_t nsectors)
#define TEST_NSECTORS 4 #define TEST_NSECTORS 4
#define TEST_SIZE (TEST_NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int)) #define TEST_SIZE (TEST_NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int))
unsigned int test_data[TEST_SIZE]; unsigned int test_data[TEST_SIZE] __attribute__ ((aligned (64)));
unsigned int res_data[TEST_SIZE]; unsigned int res_data[TEST_SIZE] __attribute__ ((aligned (64)));
int main(void) int main(void)
{ {