make clean should clean everything

Also add "make clean" for verisim"
2017-06-07 17:13:22 -07:00
parent ab87f7d487
commit 3e2b6a1d55
2 changed files with 4 additions and 1 deletions
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -59,3 +59,6 @@ $(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR)

 $(sim_debug): $(model_mk_debug) $(sim_csrcs)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
+
+clean:
+	rm -rf generated-src
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -57,6 +57,6 @@ $(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
 	+define+DEBUG -debug_pp

 clean:
-	rm -rf csrc simv-* ucli.key vc_hdrs.h
+	rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h

 .PHONY: clean