Merge pull request #7 from ucb-bar/local-fpga-support-more-modular
Separate new sys_clk and ddr2 from TSI
This commit is contained in:
Abraham Gonzalez
110
fpga/src/main/scala/vcu118/CustomOverlays.scala
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110
fpga/src/main/scala/vcu118/CustomOverlays.scala
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@@ -0,0 +1,110 @@
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package chipyard.fpga.vcu118
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import chisel3._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
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import sifive.fpgashells.shell._
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import sifive.fpgashells.ip.xilinx._
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import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.clocks._
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import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
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class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput)
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extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput)
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{
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val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) }
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shell { InModuleBody {
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shell.xdc.addPackagePin(io.p, "AW26")
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shell.xdc.addPackagePin(io.n, "AW27")
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shell.xdc.addIOStandard(io.p, "DIFF_SSTL12")
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shell.xdc.addIOStandard(io.n, "DIFF_SSTL12")
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} }
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}
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class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName)
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extends ClockInputShellPlacer[VCU118ShellBasicOverlays]
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{
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def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
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}
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case object VCU118DDR2Size extends Field[BigInt](0x40000000L * 2) // 2GB
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class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput)
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extends DDRPlacedOverlay[XilinxVCU118MIGPads](name, designInput, shellInput)
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{
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val size = p(VCU118DDRSize)
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val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.baseAddress, size))
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val mig = LazyModule(new XilinxVCU118MIG(migParams))
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val ioNode = BundleBridgeSource(() => mig.module.io.cloneType)
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val topIONode = shell { ioNode.makeSink() }
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val ddrUI = shell { ClockSourceNode(freqMHz = 200) }
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val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
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areset := designInput.wrangler := ddrUI
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// since this uses a separate clk/rst need to put an async crossing
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val asyncSink = LazyModule(new TLAsyncCrossingSink())
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val migClkRstNode = BundleBridgeSource(() => new Bundle {
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val clock = Output(Clock())
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val reset = Output(Bool())
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})
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val topMigClkRstIONode = shell { migClkRstNode.makeSink() }
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def overlayOutput = DDROverlayOutput(ddr = mig.node)
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def ioFactory = new XilinxVCU118MIGPads(size)
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InModuleBody {
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ioNode.bundle <> mig.module.io
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// setup async crossing
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asyncSink.module.clock := migClkRstNode.bundle.clock
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asyncSink.module.reset := migClkRstNode.bundle.reset
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}
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shell { InModuleBody {
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require (shell.sys_clock2.get.isDefined, "Use of DDRVCU118Overlay depends on SysClock2VCU118Overlay")
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val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0)
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val (ui, _) = ddrUI.out(0)
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val (ar, _) = areset.in(0)
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// connect the async fifo sync to sys_clock2
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topMigClkRstIONode.bundle.clock := sys.clock
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topMigClkRstIONode.bundle.reset := sys.reset
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val port = topIONode.bundle.port
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io <> port
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ui.clock := port.c0_ddr4_ui_clk
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ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
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port.c0_sys_clk_i := sys.clock.asUInt
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port.sys_rst := sys.reset // pllReset
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port.c0_ddr4_aresetn := !ar.reset
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// This was just copied from the SiFive example, but it's hard to follow.
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// The pins are emitted in the following order:
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// adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7]
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val allddrpins = Seq(
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"AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13]
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"AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg
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"AR25", "AU28", // ba[0->1]
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"BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt
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"BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15]
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"AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31]
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"BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47]
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"BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63]
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"BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7]
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"BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7]
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"BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7]
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(IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
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} }
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shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk))
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}
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class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName)
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extends DDRShellPlacer[VCU118FPGATestHarness] {
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def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
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}
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@@ -38,6 +38,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
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val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput()))
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val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput()))
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val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput()))
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val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
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val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
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val topDesign = LazyModule(p(BuildTop)(dp))
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@@ -19,7 +19,7 @@ import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
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import chipyard.{BuildSystem}
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import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency}
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import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size}
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class WithBringupPeripherals extends Config((site, here, up) => {
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case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
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@@ -38,6 +38,7 @@ class WithBringupPeripherals extends Config((site, here, up) => {
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List.empty[GPIOParams]
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}
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}
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case TSIClockMaxFrequency => 100
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case PeripheryTSIHostKey => List(
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TSIHostParams(
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serialIfWidth = 4,
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@@ -50,7 +51,7 @@ class WithBringupPeripherals extends Config((site, here, up) => {
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sourceId = IdRange(0, (1 << 13))))),
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managerPortParams = TLSlavePortParameters.v1(
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managers = Seq(TLSlaveParameters.v1(
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address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))),
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address = Seq(AddressSet(0, site(VCU118DDR2Size) - 1)),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, 64),
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@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.clocks._
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import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
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import testchipip.{TSIHostParams, TSIHostWidgetIO}
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import testchipip.{TSIHostWidgetIO}
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import chipyard.fpga.vcu118.{FMCPMap}
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@@ -152,21 +152,13 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp
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case class TSIHostShellInput()
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case class TSIHostDesignInput(
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wrangler: ClockAdapterNode,
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corePLL: PLLNode,
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tsiHostParams: TSIHostParams,
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node: BundleBridgeSource[TSIHostWidgetIO],
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vc7074gbdimm: Boolean = false
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serialIfWidth: Int,
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node: BundleBridgeSource[TSIHostWidgetIO]
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)(
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implicit val p: Parameters)
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case class TSIHostOverlayOutput(ddr: TLInwardNode)
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case class TSIHostOverlayOutput()
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trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
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class TSIHostWithDDRIO(val w: Int, val size: BigInt) extends Bundle {
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val tsi = new TSIHostWidgetIO(w)
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val ddr = new XilinxVCU118MIGPads(size)
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}
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case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil)
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abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput)
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@@ -177,43 +169,16 @@ abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHos
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case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB
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class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput)
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extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput)
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extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput)
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{
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val size = p(TSIHostVCU118DDRSize)
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// connect the DDR
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val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.tsiHostParams.targetBaseAddress, size))
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val mig = LazyModule(new XilinxVCU118MIG(migParams))
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val ioNode = BundleBridgeSource(() => mig.module.io.cloneType)
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val topIONode = shell { ioNode.makeSink() }
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val ddrUI = shell { ClockSourceNode(freqMHz = 200) }
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val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
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areset := designInput.wrangler := ddrUI
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// since this uses a separate clk/rst need to put an async crossing
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val asyncSink = LazyModule(new TLAsyncCrossingSink())
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val migClkRstNode = BundleBridgeSource(() => new Bundle {
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val clock = Output(Clock())
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val reset = Output(Bool())
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})
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val topMigClkRstIONode = shell { migClkRstNode.makeSink() }
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// connect the TSI serial
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val tlTsiSerialSink = di.node.makeSink()
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val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth))
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val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth))
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val topTSIIONode = shell { tsiIoNode.makeSink() }
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def overlayOutput = TSIHostOverlayOutput(ddr = mig.node)
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def ioFactory = new TSIHostWithDDRIO(di.tsiHostParams.serialIfWidth, size)
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def overlayOutput = TSIHostOverlayOutput()
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def ioFactory = new TSIHostWidgetIO(di.serialIfWidth)
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InModuleBody {
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// connect MIG
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ioNode.bundle <> mig.module.io
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// setup async crossing
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asyncSink.module.clock := migClkRstNode.bundle.clock
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asyncSink.module.reset := migClkRstNode.bundle.reset
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// connect TSI serial
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val tsiSourcePort = tsiIoNode.bundle
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val tsiSinkPort = tlTsiSerialSink.bundle
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@@ -225,48 +190,9 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name:
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tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid
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tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready
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}
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// connect the DDR port
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shell { InModuleBody {
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require (shell.sys_clock2.get.isDefined, "Use of TSIHostVCU118Overlay depends on SysClock2VCU118Overlay")
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val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0)
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val (ui, _) = ddrUI.out(0)
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val (ar, _) = areset.in(0)
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// connect the async fifo sink to sys_clock2
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topMigClkRstIONode.bundle.clock := sys.clock
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topMigClkRstIONode.bundle.reset := sys.reset
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val ddrPort = topIONode.bundle.port
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io.ddr <> ddrPort
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ui.clock := ddrPort.c0_ddr4_ui_clk
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ui.reset := /*!ddrPort.mmcm_locked ||*/ ddrPort.c0_ddr4_ui_clk_sync_rst
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ddrPort.c0_sys_clk_i := sys.clock.asUInt
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ddrPort.sys_rst := sys.reset // pllReset
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ddrPort.c0_ddr4_aresetn := !ar.reset
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// This was just copied from the SiFive example, but it's hard to follow.
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// The pins are emitted in the following order:
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// adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7]
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val allddrpins = Seq(
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"AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13]
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"AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg
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"AR25", "AU28", // ba[0->1]
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"BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt
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"BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15]
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"AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31]
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"BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47]
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"BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63]
|
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"BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7]
|
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"BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7]
|
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"BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7]
|
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(IOPin.of(io.ddr) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
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} }
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|
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shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk))
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}
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case object TSIClockMaxFrequency extends Field[Int](50) // in MHz
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class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput)
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extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput)
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{
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@@ -274,25 +200,25 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes
|
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shell { InModuleBody {
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// connect TSI signals
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val tsiPort = topTSIIONode.bundle
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io.tsi <> tsiPort
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io <> tsiPort
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require(di.tsiHostParams.serialIfWidth == 4)
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require(di.serialIfWidth == 4)
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val clkIo = IOPin(io.tsi.serial_clock)
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val clkIo = IOPin(io.serial_clock)
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val packagePinsWithPackageIOs = Seq(
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(FMCPMap("D8"), clkIo),
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(FMCPMap("D17"), IOPin(io.tsi.serial.out.ready)),
|
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(FMCPMap("D18"), IOPin(io.tsi.serial.out.valid)),
|
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(FMCPMap("D11"), IOPin(io.tsi.serial.out.bits, 0)),
|
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(FMCPMap("D12"), IOPin(io.tsi.serial.out.bits, 1)),
|
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(FMCPMap("D14"), IOPin(io.tsi.serial.out.bits, 2)),
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(FMCPMap("D15"), IOPin(io.tsi.serial.out.bits, 3)),
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(FMCPMap("D26"), IOPin(io.tsi.serial.in.ready)),
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(FMCPMap("D27"), IOPin(io.tsi.serial.in.valid)),
|
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(FMCPMap("D20"), IOPin(io.tsi.serial.in.bits, 0)),
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(FMCPMap("D21"), IOPin(io.tsi.serial.in.bits, 1)),
|
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(FMCPMap("D23"), IOPin(io.tsi.serial.in.bits, 2)),
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(FMCPMap("D24"), IOPin(io.tsi.serial.in.bits, 3)))
|
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(FMCPMap("D17"), IOPin(io.serial.out.ready)),
|
||||
(FMCPMap("D18"), IOPin(io.serial.out.valid)),
|
||||
(FMCPMap("D11"), IOPin(io.serial.out.bits, 0)),
|
||||
(FMCPMap("D12"), IOPin(io.serial.out.bits, 1)),
|
||||
(FMCPMap("D14"), IOPin(io.serial.out.bits, 2)),
|
||||
(FMCPMap("D15"), IOPin(io.serial.out.bits, 3)),
|
||||
(FMCPMap("D26"), IOPin(io.serial.in.ready)),
|
||||
(FMCPMap("D27"), IOPin(io.serial.in.valid)),
|
||||
(FMCPMap("D20"), IOPin(io.serial.in.bits, 0)),
|
||||
(FMCPMap("D21"), IOPin(io.serial.in.bits, 1)),
|
||||
(FMCPMap("D23"), IOPin(io.serial.in.bits, 2)),
|
||||
(FMCPMap("D24"), IOPin(io.serial.in.bits, 3)))
|
||||
|
||||
packagePinsWithPackageIOs foreach { case (pin, io) => {
|
||||
shell.xdc.addPackagePin(io, pin)
|
||||
@@ -304,7 +230,7 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes
|
||||
shell.xdc.addIOB(io)
|
||||
} }
|
||||
|
||||
shell.sdc.addClock("TSI_CLK", clkIo, 50)
|
||||
shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequency))
|
||||
shell.sdc.addGroup(pins = Seq(clkIo))
|
||||
shell.xdc.clockDedicatedRouteFalse(clkIo)
|
||||
} }
|
||||
@@ -314,21 +240,3 @@ class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val s
|
||||
extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] {
|
||||
def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
|
||||
}
|
||||
|
||||
class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput)
|
||||
extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput)
|
||||
{
|
||||
val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) }
|
||||
|
||||
shell { InModuleBody {
|
||||
shell.xdc.addPackagePin(io.p, "AW26")
|
||||
shell.xdc.addPackagePin(io.n, "AW27")
|
||||
shell.xdc.addIOStandard(io.p, "DIFF_SSTL12")
|
||||
shell.xdc.addIOStandard(io.n, "DIFF_SSTL12")
|
||||
} }
|
||||
}
|
||||
class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName)
|
||||
extends ClockInputShellPlacer[VCU118ShellBasicOverlays]
|
||||
{
|
||||
def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
|
||||
}
|
||||
|
||||
@@ -19,7 +19,7 @@ import sifive.blocks.devices.gpio._
|
||||
|
||||
import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
|
||||
|
||||
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp}
|
||||
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
|
||||
|
||||
import chipyard.{ChipTop}
|
||||
|
||||
@@ -71,21 +71,22 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
|
||||
require(dp(PeripheryTSIHostKey).size == 1)
|
||||
|
||||
// use the 2nd system clock for the 2nd DDR
|
||||
val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
|
||||
val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node
|
||||
|
||||
val ddr2PLL = dp(PLLFactoryKey)()
|
||||
ddr2PLL := sysClk2Node
|
||||
|
||||
val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
|
||||
val ddrWrangler = LazyModule(new ResetWrangler)
|
||||
val ddrGroup = ClockGroup()
|
||||
ddrClock := ddrWrangler.node := ddrGroup := ddr2PLL
|
||||
val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
|
||||
val ddr2Wrangler = LazyModule(new ResetWrangler)
|
||||
val ddr2Group = ClockGroup()
|
||||
ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL
|
||||
|
||||
val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
|
||||
|
||||
val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
|
||||
|
||||
val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth)))
|
||||
val tsiDdrNode = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)).overlayOutput.ddr
|
||||
dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb))
|
||||
|
||||
// connect 1 mem. channel to the FPGA DDR
|
||||
val inTsiParams = topDesign match { case td: ChipTop =>
|
||||
@@ -94,7 +95,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
|
||||
}
|
||||
}
|
||||
val tsiDdrClient = TLClientNode(Seq(inTsiParams.master))
|
||||
(tsiDdrNode
|
||||
(ddr2Node
|
||||
:= TLFragmenter(8,64,holdFirstDeny=true)
|
||||
:= TLCacheCork()
|
||||
:= TLAtomicAutomata(passthrough=false)
|
||||
|
||||
Reference in New Issue
Block a user