Make SRAM per port clocks optional

Connects to whatever clock ports are available

macros/src/main/scala/MacroCompiler.scala

@@ -302,7 +302,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
             case (None, None) => one
           }
           selectRegs(ref.name) = WRef(regName, tpe)
-          stmts += DefRegister(NoInfo, regName, tpe, WRef(port.clock.name), zero, WRef(regName))
+          stmts += DefRegister(NoInfo, regName, tpe, WRef(port.clock.get.name), zero, WRef(regName))
           stmts += Connect(NoInfo, WRef(regName), Mux(enable, WRef(nodeName), WRef(regName), tpe))
         }
       }
@@ -348,9 +348,11 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
 
           // Clock port mapping
           /* Palmer: FIXME: I don't handle memories with read/write clocks yet. */
-          stmts += connectPorts(WRef(memPort.src.clock.name),
-                                libPort.src.clock.name,
-                                libPort.src.clock.polarity)
+          /* Colin not all libPorts have clocks but all memPorts do*/
+          libPort.src.clock.foreach { cPort =>
+            stmts += connectPorts(WRef(memPort.src.clock.get.name),
+                                       cPort.name,
+                                       cPort.polarity) }
 
           // Adress port mapping
           /* Palmer: The address port to a memory is just the low-order bits of

macros/src/main/scala/SynFlops.scala

@@ -38,7 +38,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
     )
 
     val readConnects = lib.readers.zipWithIndex flatMap { case (r, i) =>
-      val clock = portToExpression(r.src.clock)
+      val clock = portToExpression(r.src.clock.get)
       val address = portToExpression(r.src.address)
       val enable = (r.src chipEnable, r.src readEnable) match {
         case (Some(en_port), Some(re_port)) =>
@@ -63,7 +63,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
     }
 
     val writeConnects = lib.writers.zipWithIndex flatMap { case (w, i) =>
-      val clock = portToExpression(w.src.clock)
+      val clock = portToExpression(w.src.clock.get)
       val address = portToExpression(w.src.address)
       val enable = (w.src.chipEnable, w.src.writeEnable) match {
         case (Some(en), Some(we)) =>
@@ -95,7 +95,7 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
     }
 
     val readwriteConnects = lib.readwriters.zipWithIndex flatMap { case (rw, i) =>
-      val clock = portToExpression(rw.src.clock)
+      val clock = portToExpression(rw.src.clock.get)
       val address = portToExpression(rw.src.address)
       val wmode = rw.src.writeEnable match {
         case Some(we) => portToExpression(we)

macros/src/main/scala/Utils.scala

@@ -24,8 +24,8 @@ class FirrtlMacroPort(port: MacroPort) {
 
   // Bundle representing this macro port.
   val tpe = BundleType(Seq(
-    Field(port.clock.name, Flip, ClockType),
     Field(port.address.name, Flip, addrType)) ++
+    (port.clock map (p => Field(p.name, Flip, ClockType))) ++
     (port.input map (p => Field(p.name, Flip, dataType))) ++
     (port.output map (p => Field(p.name, Default, dataType))) ++
     (port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++
@@ -93,7 +93,7 @@ object Utils {
         MacroPort(
           width=Some(width), depth=Some(depth),
           address=PolarizedPort(s"${portName}_addr", ActiveHigh),
-          clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
+          clock=Some(PolarizedPort(s"${portName}_clk", PositiveEdge)),
           chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
           output=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
         ) }
@@ -103,7 +103,7 @@ object Utils {
         MacroPort(
           width=Some(width), depth=Some(depth),
           address=PolarizedPort(s"${portName}_addr", ActiveHigh),
-          clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
+          clock=Some(PolarizedPort(s"${portName}_clk", PositiveEdge)),
           writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
           input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
         ) }
@@ -113,7 +113,7 @@ object Utils {
         MacroPort(
           width=Some(width), depth=Some(depth),
           address=PolarizedPort(s"${portName}_addr", ActiveHigh),
-          clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
+          clock=Some(PolarizedPort(s"${portName}_clk", PositiveEdge)),
           writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
           maskPort=Some(PolarizedPort(s"${portName}_mask", ActiveHigh)),
           maskGran=maskGran,
@@ -125,7 +125,7 @@ object Utils {
         MacroPort(
           width=Some(width), depth=Some(depth),
           address=PolarizedPort(s"${portName}_addr", ActiveHigh),
-          clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
+          clock=Some(PolarizedPort(s"${portName}_clk", PositiveEdge)),
           chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
           writeEnable=Some(PolarizedPort(s"${portName}_wmode", ActiveHigh)),
           input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
@@ -137,7 +137,7 @@ object Utils {
         MacroPort(
           width=Some(width), depth=Some(depth),
           address=PolarizedPort(s"${portName}_addr", ActiveHigh),
-          clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
+          clock=Some(PolarizedPort(s"${portName}_clk", PositiveEdge)),
           chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
           writeEnable=Some(PolarizedPort(s"${portName}_wmode", ActiveHigh)),
           maskPort=Some(PolarizedPort(s"${portName}_wmask", ActiveHigh)),