wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/ucb-bar/chipyard into vlsi-tutorial

Browse Source
This commit is contained in:
Nayiri Krzysztofowicz
2023-03-10 15:59:13 -08:00
parent b52cad6123 a8c9c8271e
commit 47f84e97b4
4 changed files with 26 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -242,3 +242,14 @@ class WithDefaultFireSimBridges extends Config(
new WithTracerVBridge ++
new WithFireSimIOCellModels
)
// Shorthand to register all of the provided mmio-only bridges above
class WithDefaultMMIOOnlyFireSimBridges extends Config(
new WithSerialBridge ++
new WithUARTBridge ++
new WithBlockDeviceBridge ++
new WithFASEDBridge ++
new WithFireSimMultiCycleRegfile ++
new WithFireSimFAME5 ++
new WithFireSimIOCellModels
)

6
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -282,3 +282,9 @@ class FireSimNoMemPortConfig extends Config(
new testchipip.WithBackingScratchpad ++
new WithFireSimConfigTweaks ++
new chipyard.RocketConfig)
class FireSimRocketMMIOOnlyConfig extends Config(
new WithDefaultMMIOOnlyFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.RocketConfig)

10
vlsi/Makefile
View File

@@ -46,9 +46,9 @@ VLSI_MODEL_DUT_NAME ?= chiptop
# If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
else
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP)
endif
#########################################################################################
@@ -118,6 +118,12 @@ endif
$(SYN_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " input_files:" >> $@
for x in $$(cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@

2
vlsi/sim.mk
View File

@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $$(cat $(sim_common_files)); do \
for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@