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Merge pull request #277 from ucb-bar/hetero-linux

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FireSim Support for Hetero-Linux + FireSim Cleanup
This commit is contained in:
Abraham Gonzalez
2019-10-09 22:14:50 -07:00
committed by GitHub
parent f7a84f4900 f0cd542095
commit 480397ea09
7 changed files with 65 additions and 106 deletions
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2
.circleci/defaults.sh
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@@ -48,5 +48,5 @@ mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha"
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"

2
generators/boom

Submodule generators/boom updated: 7b68d748b6...2a0ea2e7ac

13
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -195,6 +195,19 @@ class FireSimBoomQuadCoreConfig extends Config(
new WithNDuplicatedBoomCores(4) ++
new FireSimBoomConfig)
//**********************************************************************************
//* Heterogeneous Configurations
//*********************************************************************************/
// dual core config (rocket + small boom)
class FireSimRocketBoomConfig extends Config(
new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
new boom.common.WithRenumberHarts ++ // fix hart numbering
new boom.common.WithSmallBooms ++ // change single BOOM to small
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
new FireSimBoomConfig
)
//**********************************************************************************
//* Supernode Configurations
//*********************************************************************************/

42
generators/firechip/src/main/scala/TargetMixins.scala
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@@ -9,11 +9,14 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.util._
import freechips.rocketchip.tile.RocketTile
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.TracedInstruction
import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
import midas.targetutils.MemModelAnnotation
import boom.common.BoomTile
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
* TracerV bridge can match on.
@@ -47,28 +50,25 @@ trait HasTraceIOImp extends LazyModuleImp {
}
}
// Prevent MIDAS from synthesizing assertions in the dummy TLB included in BOOM
trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
}
trait CanHaveMultiCycleRegfileImp {
val outer: utilities.HasBoomAndRocketTiles
val boomCores = outer.boomTiles.map(tile => tile.module.core)
boomCores.foreach({ core =>
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
outer.tiles.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
}
})
outer.rocketTiles.foreach({ tile =>
annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
})
case b: BoomTile => {
val core = b.module.core
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
case _ => Nil
}
}
}
}

53
generators/firechip/src/main/scala/Targets.scala
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@@ -86,61 +86,8 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule
with HasTraceIOImp
with CanHaveMultiCycleRegfileImp
class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
class FireBoomDUT(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
with HasPeripherySerial
with HasPeripheryUART
with HasPeripheryIceNIC
with HasPeripheryBlockDevice
with HasTraceIO
{
override lazy val module = new FireBoomModuleImp(this)
}
class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp
with HasPeripheryIceNICModuleImpValidOnly
with HasPeripheryBlockDeviceModuleImp
with HasTraceIOImp
with ExcludeInvalidBoomAssertions
with CanHaveMultiCycleRegfileImp
class FireBoom(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomDUT)
class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
with HasPeripherySerial
with HasPeripheryUART
with HasPeripheryBlockDevice
with HasTraceIO
{
override lazy val module = new FireBoomNoNICModuleImp(this)
}
class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp
with HasPeripheryBlockDeviceModuleImp
with HasTraceIOImp
with ExcludeInvalidBoomAssertions
with CanHaveMultiCycleRegfileImp
class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomNoNICDUT)
class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
with HasHierarchicalBusTopology
with HasTraceGenTiles

57
generators/utilities/src/main/scala/Subsystem.scala
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@@ -21,7 +21,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey}
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
trait HasBoomAndRocketTiles extends HasTiles
@@ -34,49 +34,49 @@ trait HasBoomAndRocketTiles extends HasTiles
protected val rocketTileParams = p(RocketTilesKey)
protected val boomTileParams = p(BoomTilesKey)
// crossing can either be per tile or global (aka only 1 crossing specified)
private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
val allTilesInfo = (rocketTileParams ++ boomTileParams) zip (rocketCrossings ++ boomCrossings)
// Make a tile and wire its nodes into the system,
// according to the specified type of clock crossing.
// Note that we also inject new nodes into the tile itself,
// also based on the crossing type.
val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
// This MUST be performed in order of hartid
// There is something weird with registering tile-local interrupt controllers to the CLINT.
// TODO: investigate why
val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
case (param, crossing) => {
val (tile, rocketLogicalTree) = param match {
case r: RocketTileParams => {
val t = LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
(t, t.rocketLogicalTree)
}
case b: BoomTileParams => {
val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
(t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
}
}
connectMasterPortsToSBus(tile, crossing)
connectSlavePortsToCBus(tile, crossing)
connectMasterPortsToSBus(rocket, crossing)
connectSlavePortsToCBus(rocket, crossing)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree)
rocket
}
val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
connectMasterPortsToSBus(boom, crossing)
connectSlavePortsToCBus(boom, crossing)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree)
boom
}
// combine tiles and connect interrupts based on the order of harts
val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map {
tile => {
connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
tile
}
}
def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
(boomTiles map { t => t.module.core.coreMonitorBundle}).toList
def coreMonitorBundles = tiles.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle
}.toList
}
trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
@@ -88,7 +88,6 @@ trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
class Subsystem(implicit p: Parameters) extends BaseSubsystem
with HasBoomAndRocketTiles
{
val tiles = boomAndRocketTiles
override lazy val module = new SubsystemModuleImp(this)
def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil

2
sims/firesim

Submodule sims/firesim updated: afd51ab7a8...a55d4ae9ee