Makefile fixes, but sim still doesn't work
This commit is contained in:
Harrison Liew
committed by
abejgonzalez
abejgonzalez
parent
1dcc7bd9f5
commit
48539353b0
@@ -49,6 +49,8 @@ This is done by the following:
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conda install -n base conda-lock
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conda activate base
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.. Note:: We also recommended switching to `libmamba <https://www.anaconda.com/blog/a-faster-conda-for-a-growing-community>`__ for much faster dependency solving.
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Setting up the Chipyard Repo
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-------------------------------------------
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@@ -101,6 +103,8 @@ This file activates the conda environment created in ``build-setup.sh`` and sets
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Once the script is run, the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables will be set properly for the toolchain requested.
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You can source this file in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment:
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.. Note:: If you are on a Mac or a RHEL/CentOS-based Linux distribution, you must deactivate the base conda environment with ``conda deactivate`` first before proceeding. You may also choose to keep it deactivated by default with ``conda config --set auto_activate_base false``. See this `issue <https://github.com/conda/conda/issues/9392>`__ for more details.
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.. code-block:: shell
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source ./env.sh
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@@ -150,6 +150,5 @@ fi
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cat << EOT >> env.sh
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# line auto-generated by init-submodules-no-riscv-tools.sh
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__DIR="$RDIR"
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PATH=\$__DIR/bin:\$PATH
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PATH=\$__DIR/software/firemarshal:\$PATH
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EOT
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@@ -8,6 +8,7 @@
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base_dir=$(abspath ..)
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vlsi_dir=$(abspath .)
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sim_dir=$(abspath .)
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site_packages_dir=$(shell python3 -c "import site; print(site.getsitepackages()[0])")
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#########################################################################################
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# include shared variables
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@@ -21,7 +22,7 @@ include $(base_dir)/variables.mk
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sim_name ?= vcs # needed for GenerateSimFiles, but is unused
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tech_name ?= asap7
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tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
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$(vlsi_dir)/hammer/hammer/technology/$(tech_name), \
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$(site_packages_dir)/hammer/technology/$(tech_name), \
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$(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/technology/$(tech_name))
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SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
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SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
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@@ -42,7 +43,7 @@ HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
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./example-vlsi-sky130,\
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./example-vlsi)
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VLSI_TOP ?= $(TOP)
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VLSI_HARNESS_DUT_NAME ?= chiptop
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VLSI_MODEL_DUT_NAME ?= chiptop
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# If overriding, this should be relative to $(vlsi_dir)
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VLSI_OBJ_DIR ?= build
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ifneq ($(CUSTOM_VLOG),)
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@@ -54,23 +55,19 @@ endif
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#########################################################################################
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# general rules
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#########################################################################################
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ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
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extra_v_includes = $(build_dir)/EICG_wrapper.v
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# TODO: get all the top blackboxes only
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extra_v_includes = $(build_dir)/EICG_wrapper.v $(build_dir)/gen-collateral/IOCell.v
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ifneq ($(CUSTOM_VLOG), )
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VLSI_RTL = $(CUSTOM_VLOG)
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VLSI_BB = /dev/null
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else
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VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
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VLSI_BB = $(sim_top_blackboxes)
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VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST)) $(TOP_SMEMS_FILE) $(extra_v_includes)
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endif
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.PHONY: default verilog
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.PHONY: default
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default: all
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all: drc lvs
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verilog: $(ALL_RTL)
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#########################################################################################
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# import other necessary rules and variables
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#########################################################################################
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@@ -104,29 +101,17 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
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#########################################################################################
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include $(base_dir)/vcs.mk
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SIM_FILE_REQS += \
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$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
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# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
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$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
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cp -f $^ $(build_dir)
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$(foreach file,\
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$^,\
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$(if $(filter %.h,$(file)),\
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,\
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echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
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SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
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SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
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SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
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include $(vlsi_dir)/sim.mk
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$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
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$(SIM_CONF): $(sim_common_files)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " top_module: $(VLSI_TOP)" >> $@
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echo " input_files:" >> $@
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for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \
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for x in $(shell cat $(sim_common_files)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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@@ -161,9 +146,9 @@ $(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $
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ifneq ($(BINARY), )
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echo " benchmarks: ['$(BINARY)']" >> $@
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endif
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echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
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echo " tb_dut: 'TestDriver.testHarness.$(VLSI_MODEL_DUT_NAME)'" >> $@
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$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
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$(SIM_DEBUG_CONF): $(sim_common_files)
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mkdir -p $(dir $@)
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mkdir -p $(output_dir)
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echo "sim.inputs:" > $@
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@@ -186,7 +171,7 @@ else
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echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
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endif
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$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
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$(SIM_TIMING_CONF): $(sim_common_files)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " defines: ['NTC']" >> $@
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@@ -195,10 +180,10 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_f
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POWER_CONF = $(OBJ_DIR)/power-inputs.yml
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include $(vlsi_dir)/power.mk
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$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
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$(POWER_CONF): $(VLSI_RTL)
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mkdir -p $(dir $@)
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echo "power.inputs:" > $@
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echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
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echo " tb_dut: 'testHarness/$(VLSI_MODEL_DUT_NAME)'" >> $@
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echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
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ifneq ($(BINARY), )
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echo " waveforms: [" >> $@
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@@ -223,18 +208,12 @@ ifeq ($(CUSTOM_VLOG), )
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GENERATED_CONFS += $(SRAM_CONF)
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endif
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$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
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$(SYN_CONF): $(VLSI_RTL)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " input_files:" >> $@
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for x in $(VLSI_RTL); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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echo "synthesis.inputs:" >> $@
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echo " top_module: $(VLSI_TOP)" >> $@
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echo " input_files:" >> $@
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for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
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for x in $(VLSI_RTL); do \
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echo ' - "'$$x'"' >> $@; \
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done
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@@ -1,7 +1,5 @@
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# SRAM Compiler compiler options
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vlsi.core.sram_generator_tool: "hammer.technology.<tech_name>.sram_compiler"
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# Tool options. Replace with your tool plugin of choice.
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vlsi.core.build_system: make
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# Genus options
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vlsi.core.synthesis_tool: "hammer.synthesis.genus"
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synthesis.genus.version: "211"
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@@ -17,9 +15,8 @@ vlsi.core.lvs_tool: "hammer.lvs.calibre"
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lvs.calibre.version: "2022.2_24.16"
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# VCS options
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vlsi.core.sim_tool: "hammer.sim.vcs"
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sim.vcs.version: "T-2022.06-SP2"
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sim.vcs.version: "S-2021.09-SP1-1"
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# Voltus options
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vlsi.core.power_tool: "hammer.power.voltus"
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vlsi.core.power_tool_path_meta: "append"
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power.voltus.version: "211_ISR3"
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# NOTE (about VCS+Voltus versions): if using FSDB, the VCS version should be approx 2 years older than the Voltus version for compatibility
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@@ -17,7 +17,7 @@ ifeq ($(tutorial),sky130-commercial)
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tech_name ?= sky130
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CONFIG ?= TinyRocketConfig
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TOOLS_CONF ?= example-tools.yml
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TECH_CONF ?= hammer/e2e/pdks/sky130-bwrc.yml
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TECH_CONF ?= example-sky130.yml
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DESIGN_CONF ?= example-designs/sky130-commercial.yml
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EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
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