ADD: add support for multiple peripherals of same kind
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@@ -6,7 +6,8 @@ import chisel3.util.{log2Up}
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import org.chipsalliance.cde.config.{Config}
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import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
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import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
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import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
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import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
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import freechips.rocketchip.stage.phases.TargetDirKey
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tile.{XLen}
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@@ -14,6 +15,7 @@ import freechips.rocketchip.tile.{XLen}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.i2c._
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import testchipip._
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@@ -22,41 +24,65 @@ import chipyard.{ExtTLMem}
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// Set the bootrom to the Chipyard bootrom
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class WithBootROM extends Config((site, here, up) => {
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case BootROMLocated(x) => up(BootROMLocated(x), site)
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.map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"))
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.map(_.copy(
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address = 0x10000,
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size = 0x10000,
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hang = 0x10040,
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contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"
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))
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})
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// DOC include start: gpio config fragment
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class WithGPIO extends Config((site, here, up) => {
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case PeripheryGPIOKey => Seq(
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GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
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class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => {
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case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq(
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GPIOParams(address = address, width = width, includeIOF = false))
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})
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// DOC include end: gpio config fragment
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class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
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case PeripheryUARTKey => Seq(
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UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
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})
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class WithNoUART extends Config((site, here, up) => {
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case PeripheryUARTKey => Nil
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})
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class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => {
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case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq(
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UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
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})
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class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
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case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
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})
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class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
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class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => {
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// Note: the default size matches freedom with the addresses below
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case PeripherySPIFlashKey => Seq(
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SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size))
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case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq(
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SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size))
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})
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class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => {
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case PeripherySPIKey => up(PeripherySPIKey) ++ Seq(
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SPIParams(rAddress = address))
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})
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class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => {
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case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq(
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I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing())
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)
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})
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class WithNoDebug extends Config((site, here, up) => {
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case DebugModuleKey => None
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})
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class WithDMIDTM extends Config((site, here, up) => {
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case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI))
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})
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class WithNoDebug extends Config((site, here, up) => {
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case DebugModuleKey => None
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class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => {
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case JtagDTMKey => new JtagDTMConfig (
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idcodeVersion = idcodeVersion,
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idcodePartNum = partNum,
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idcodeManufId = manufId,
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debugIdleCycles = debugIdleCycles)
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})
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class WithTLBackingMemory extends Config((site, here, up) => {
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