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common.mk: doc EXTRA_SIM_OUT_NAME

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Hansung Kim
2024-05-05 20:06:45 -07:00
parent 1173383003
commit 486cde650a
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common.mk
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@@ -16,6 +16,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" EXTRA_SIM_OUT_NAME = additional suffix appended to the simulation .out log filename" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \