bump radiance and cleanup configs; add print util script
This commit is contained in:
Richard Yan
@@ -3,21 +3,10 @@ package chipyard
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import chipyard.config.AbstractConfig
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import chipyard.stage.phases.TargetDirKey
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import freechips.rocketchip.devices.tilelink.BootROMLocated
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import freechips.rocketchip.prci.AsynchronousCrossing
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import freechips.rocketchip.resources.BigIntHexContext
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import freechips.rocketchip.subsystem._
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import org.chipsalliance.cde.config.Config
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import radiance.memory._
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import radiance.subsystem.{RadianceGemminiDataType, WithRadianceSharedMem}
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class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => {
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case RadianceROMsLocated() => Some(up(RadianceROMsLocated()).getOrElse(Seq()) ++
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Seq(RadianceROMParams(
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address = address,
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size = size,
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contentFileName = filename
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)))
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})
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import radiance.subsystem.RadianceGemminiDataType
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class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => {
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case BootROMLocated(x) => up(BootROMLocated(x))
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@@ -33,7 +22,13 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
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// Radiance Configs
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// ----------------
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class RadianceBaseConfig(argsBinFilename: String = "args.bin") extends Config(
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// aliases for virgo
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class VirgoConfig extends RadianceClusterConfig
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class VirgoFP16Config extends RadianceFP16ClusterConfig
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class VirgoSynConfig extends RadianceClusterSynConfig
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class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig
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class RadianceBaseConfig extends Config(
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// NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in
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// the verilog source as well!
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new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++
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@@ -59,28 +54,15 @@ class RadianceFP16ClusterConfig extends Config(
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class RadianceClusterConfig extends Config(
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// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
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new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
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new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
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// new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
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new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++
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// new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++
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//
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// note to hansung: somehow I don't have serializeUnaligned in my radiance subsystem files. I'll
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// re-implement this with all the options instead of just this one
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new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
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new radiance.subsystem.WithRadianceCluster(0) ++
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new RadianceBaseConfig)
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class RadianceClusterSmallConfig extends Config(
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// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
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new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
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new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), useVxCache = false) ++
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new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: true
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
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new radiance.subsystem.WithRadianceCluster(0) ++
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new RadianceBaseConfig)
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class RadianceClusterSmem16KConfig extends Config(
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new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++
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new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++
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@@ -112,27 +94,6 @@ class RadianceBigLittleClusterConfig extends Config(
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new radiance.subsystem.WithRadianceCluster(0) ++
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new RadianceBaseConfig)
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class RadianceClusterConfig0 extends Config(
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new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++
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// new radiance.subsystem.WithCoalescer(nNewSrcIds = 8, enable = false) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++
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new radiance.subsystem.WithRadianceCluster(0) ++
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new RadianceBaseConfig)
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class RadianceClusterConfig1 extends Config(
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new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++
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new radiance.subsystem.WithRadianceCluster(0) ++
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new RadianceBaseConfig("args.1.bin"))
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class RadianceClusterConfig2 extends Config(
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new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++
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new radiance.subsystem.WithRadianceCluster(0) ++
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new RadianceBaseConfig("args.2.bin"))
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class RadianceClusterSynConfig extends Config(
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new radiance.subsystem.WithRadianceSimParams(false) ++
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new RadianceClusterConfig)
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@@ -145,12 +106,6 @@ class RadianceBigLittleClusterSynConfig extends Config(
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new radiance.subsystem.WithRadianceSimParams(false) ++
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new RadianceBigLittleClusterConfig)
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class RadianceGemminiConfig extends Config(
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new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
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new RadianceBaseConfig)
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class RadianceNoCacheConfig extends Config(
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new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++
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@@ -161,24 +116,6 @@ class RadianceNoCoalConfig extends Config(
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new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
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new RadianceBaseConfig)
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class RadianceNoCacheNoCoalConfig extends Config(
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new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
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new RadianceBaseConfig)
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class RadianceLargeConfig extends Config(
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new radiance.subsystem.WithRadianceCores(4, useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
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new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
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new RadianceBaseConfig)
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class RadianceNoROMConfig extends Config(
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new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new WithExtMemSize(BigInt("80000000", 16)) ++
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new WithRadBootROM() ++
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new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
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new AbstractConfig)
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class RadianceFuzzerConfig extends Config(
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new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++
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@@ -187,32 +124,3 @@ class RadianceFuzzerConfig extends Config(
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new chipyard.harness.WithCeaseSuccess ++
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new chipyard.iobinders.WithCeasePunchThrough ++
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new AbstractConfig)
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class RadianceOldCacheConfig extends Config(
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new radiance.subsystem.WithRadianceCores(1, useVxCache = true) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new WithExtMemSize(BigInt("80000000", 16)) ++
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new WithRadBootROM() ++
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new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
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new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
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new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
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new AbstractConfig
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)
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// --------------------
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// Rocket-based Configs
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// --------------------
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class RocketDummyVortexConfig extends Config(
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new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
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new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
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new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 16) ++
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new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
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new WithExtMemSize(BigInt("80000000", 16)) ++
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new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new AbstractConfig)
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class RocketGPUConfig extends Config(
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new radiance.subsystem.WithNCustomSmallRocketCores(2) ++
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new chipyard.config.AbstractConfig)
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Submodule generators/radiance updated: b335132c34...2929a84ecc
142
sims/vcs/pprint
Executable file
142
sims/vcs/pprint
Executable file
@@ -0,0 +1,142 @@
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#!/usr/bin/env python3
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import sys
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import signal
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import re
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PRINT_BUF = 0x20000 / 4
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def translator(line):
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if 'core-req-wr' in line:
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# Check rs1_data's last element condition
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rs1_data_start = line.find('addr={') + len('addr={')
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rs1_data_end = line.find('}', rs1_data_start)
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rs1_data_elts = line[rs1_data_start:rs1_data_end].split(', ')
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byteen_start = line.find('byteen={') + len('byteen={')
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byteen_end = line.find('}', byteen_start)
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byteen_elts = line[byteen_start:byteen_end].split(', ')
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rs2_data_start = line.find('data={') + len('data={')
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rs2_data_end = line.find('}', rs2_data_start)
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rs2_data_elts = line[rs2_data_start:rs2_data_end].split(', ')
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# print(rs1_data_last_element)
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for rs1, rs2, byteen in zip(rs1_data_elts, rs2_data_elts, byteen_elts):
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if int(rs1, 16) >> 18 == 0xff0:
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offset = (int(rs1, 16) - PRINT_BUF) % 65536
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if offset < 0 or offset >= 1024:
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continue
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else:
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offset = offset % 16384
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# Extract rs2_data's last element
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hex_value = rs2[2:] # Remove the '0x' prefix
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if "x" in hex_value:
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continue
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byteen_int = int(byteen, 16)
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hex_value = "0" * (8 - len(hex_value)) + hex_value
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bytes_object = bytes.fromhex(hex_value) # .replace(b"\x00", b"")
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masked_bytes_list = []
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assert(len(bytes_object) == 4)
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for i, byte in enumerate(bytes_object[::-1]):
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if byteen_int & (1 << i):
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masked_bytes_list.append(byte)
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reversed_bytes = bytes(masked_bytes_list)
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# print(reversed_bytes.decode('utf-8', errors="ignore"))
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try:
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return reversed_bytes.decode('ascii', errors="ignore")
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except UnicodeDecodeError:
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return ""
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def timestamp_parser(line):
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parts = line.strip().split()
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if parts:
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return parts[0][:-1]
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else:
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return ""
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sim_started = False
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sim_ended = False
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def signal_handler(sig, frame):
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if sim_started:
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print("\033[u")
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sys.exit(0)
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def main():
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signal.signal(signal.SIGINT, signal_handler)
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current_timestamp = ""
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re_start_num = re.compile(r"^\s*[0-9]+:")
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print("\033[2J\033[H")
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ts_countdown = 100
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global sim_started, sim_ended
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perf_counters = False
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hang_detector = 0
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for line in sys.stdin:
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line = line.rstrip('\n')
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ts_countdown -= 1
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if "Chronologic VCS simulator" in line:
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sim_started = True
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sim_nontrace = re.match(re_start_num, line) is None
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if "has no more active warps" in line:
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sim_ended = True
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if "====================CORE" in line:
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perf_counters = True
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if hang_detector >= 8:
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print("\n\033[3mpossible hang detected\033[0m\n")
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if (not sim_started) or sim_ended:
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if "has no more active warps" not in line:
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print(line)
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continue
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elif sim_started and (not sim_ended):
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if sim_nontrace:
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if not perf_counters:
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print(line)
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elif line.startswith("dcache stores:"):
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perf_counters = False
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hang_detector += 1
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continue
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else:
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hang_detector = 0
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if ts_countdown == 0:
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timestamp = timestamp_parser(line)
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if timestamp:
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current_timestamp = timestamp
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# Save cursor position
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print("\033[s", end='')
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# Move cursor to top-left corner, clear line, bold, timestamp, unbold
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print("\033[H\033[2K\033[1", current_timestamp, "\033[0m", end='')
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# Restore cursor position
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print("\033[u", end='')
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ts_countdown = 100
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else:
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ts_countdown = 1
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ts_countdown -= 1
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translated_line = translator(line)
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if translated_line:
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print(translated_line, end='')
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sys.stdout.flush()
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print("")
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if __name__ == '__main__':
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main()
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