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Use series of pipe Queues instead of ShiftQueue for adding AXI4 memory delay

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This commit is contained in:
Jerry Zhao
2021-02-09 00:47:10 -08:00
parent 235b1e5dfd
commit 4c11e170b8
1 changed files with 5 additions and 5 deletions
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10
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -159,11 +159,11 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind
}
if (additionalLatency > 0) {
withClockAndReset (port.clock, port.reset) {
mem.io.axi.aw <> ShiftQueue(Decoupled(port.bits.aw), additionalLatency)
mem.io.axi.w <> ShiftQueue(Decoupled(port.bits.w ), additionalLatency)
port.bits.b <> ShiftQueue(Decoupled(mem.io.axi.b), additionalLatency)
mem.io.axi.ar <> ShiftQueue(Decoupled(port.bits.ar), additionalLatency)
port.bits.r <> ShiftQueue(Decoupled(mem.io.axi.r), additionalLatency)
mem.io.axi.aw <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.aw))((t, _) => Queue(t, 1, pipe=true))
mem.io.axi.w <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.w ))((t, _) => Queue(t, 1, pipe=true))
port.bits.b <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.b))((t, _) => Queue(t, 1, pipe=true))
mem.io.axi.ar <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.ar))((t, _) => Queue(t, 1, pipe=true))
port.bits.r <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.r))((t, _) => Queue(t, 1, pipe=true))
}
}
mem.io.clock := port.clock