update rocket-chip again

Makefrag

@@ -11,8 +11,9 @@ lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
 
 libs: $(rocketchip_stamp) $(extra_stamps)
 
+ROCKETCHIP_JAR = $(lib_dir)/rocketchip_2.11-1.2.jar
 FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar
-FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
+FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKETCHIP_JAR):$(FIRRTL_JAR) firrtl.Driver
 
 $(rocketchip_stamp): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)) $(FIRRTL_JAR)
 	cd $(ROCKETCHIP_DIR) && $(SBT) pack

src/main/scala/example/Top.scala

@@ -8,7 +8,7 @@ import freechips.rocketchip.util.DontTouch
 import testchipip._
 
 class ExampleTop(implicit p: Parameters) extends RocketSubsystem
-    with HasMasterAXI4MemPort
+    with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasSystemErrorSlave
     with HasSyncExtInterrupts
@@ -19,7 +19,7 @@ class ExampleTop(implicit p: Parameters) extends RocketSubsystem
 
 class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketSubsystemModuleImp(l)
     with HasRTCModuleImp
-    with HasMasterAXI4MemPortModuleImp
+    with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
     with HasExtInterruptsModuleImp
     with HasNoDebugModuleImp

verisim/Makefile

@@ -22,9 +22,12 @@ include $(sim_dir)/Makefrag-verilator
 
 long_name = $(PROJECT).$(MODEL).$(CONFIG)
 
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+
 sim_vsrcs = \
 	$(build_dir)/$(long_name).v \
-	$(ROCKETCHIP_DIR)/vsrc/AsyncResetReg.v \
+	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
+	$(rocketchip_vsrc_dir)/plusarg_reader.v \
 	$(testchip_vsrcs)
 
 sim_csrcs = \

verisim/Makefrag-verilator

@@ -24,6 +24,8 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
 	mkdir -p $(dir $@)
 	wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
 
+rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc
+
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 VERILATOR_FLAGS := --top-module $(MODEL) \
@@ -32,4 +34,4 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   --output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
   -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/rocket-chip/csrc/verilator.h"
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"

vsim/Makefile

@@ -16,11 +16,13 @@ debug: $(simv_debug)
 
 include $(base_dir)/Makefrag
 
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+
 sim_vsrcs = \
 	$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \
-	$(ROCKETCHIP_DIR)/vsrc/TestDriver.v \
-	$(ROCKETCHIP_DIR)/vsrc/AsyncResetReg.v \
-	$(ROCKETCHIP_DIR)/vsrc/plusarg_reader.v \
+	$(rocketchip_vsrc_dir)/TestDriver.v \
+	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
+	$(rocketchip_vsrc_dir)/plusarg_reader.v \
 	$(testchip_vsrcs)
 
 sim_csrcs = \