have core 0 interrupt other cores

bootrom/Makefile

@@ -1,10 +1,13 @@
 bootrom_img = bootrom.img
+bootrom_dump = bootrom.dump
 
 GCC=riscv64-unknown-elf-gcc
 OBJCOPY=riscv64-unknown-elf-objcopy
 OBJDUMP=riscv64-unknown-elf-objdump
 
-all: $(bootrom_img)
+img: $(bootrom_img)
+
+dump: $(bootrom_dump)
 
 %.img: %.elf
 	$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@

bootrom/bootrom.S

@@ -3,9 +3,20 @@
 .section .text.start, "ax", @progbits
 .globl _start
 _start:
-  csrr a0, mhartid
-  sll a0, a0, 2 // offset for hart msip
   li a1, 0x2000000 // base address of clint
+  csrr a0, mhartid
+  bnez a0, boot_core
+
+  addi a2, a1, 4
+  li a3, 1
+interrupt_loop:
+  sw a3, 0(a2)
+  addi a2, a2, 4
+  lw a3, -4(a2)
+  bnez a3, interrupt_loop
+
+boot_core:
+  sll a0, a0, 2 // offset for hart msip
   add a0, a0, a1
   sw zero, 0(a0) // clear the interrupt
   li a0, DRAM_BASE // program reset vector

src/main/scala/example/Configs.scala

@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels}
+import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores}
 import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
@@ -54,3 +54,7 @@ class WithFourTrackers extends WithNBlockDeviceTrackers(4)
 
 class WithTwoMemChannels extends WithNMemoryChannels(2)
 class WithFourMemChannels extends WithNMemoryChannels(4)
+
+class DualCoreConfig extends Config(
+  // Core gets tacked onto existing list
+  new WithNBigCores(1) ++ new DefaultExampleConfig)