Fix compile breaking due to merge conflict

2023-02-02 10:01:35 -08:00
parent e732fdf130
commit 5525cd7571
1 changed files with 5 additions and 0 deletions
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -58,6 +58,11 @@ case class SpikeCoreParams(
  val rasEntries = 0
  val btbEntries = 0
  val bhtEntries = 0
+  val traceHasWdata = false
+  val useBitManip = false
+  val useBitManipCrypto = false
+  val useCryptoNIST = false
+  val useCryptoSM = false

  override def vLen = 128
  override def vMemDataBits = 128