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Add WithUARTInitBaud/fix firesim uart configs

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This commit is contained in:
Jerry Zhao
2023-06-15 10:20:52 -07:00
parent 0de74215a1
commit 563897ba22
2 changed files with 6 additions and 2 deletions
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4
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -72,6 +72,10 @@ class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site,
case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
})
class WithUARTInitBaudRate(baudrate: BigInt = 115200) extends Config ((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(initBaudRate=baudrate))
})
/**
* Config fragment for adding a SPI peripheral device with Execute-in-Place capability to the SoC
*

4
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -92,7 +92,7 @@ class WithFireSimDesignTweaks extends Config(
// Optional: reduce the width of the Serial TL interface
new testchipip.WithSerialTLWidth(4) ++
// Required*: Scale default baud rate with periphery bus frequency
new chipyard.config.WithUART(BigInt(3686400L)) ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
// Optional: Adds IO to attach tracerV bridges
new chipyard.config.WithTraceIO ++
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
@@ -241,7 +241,7 @@ class FireSimSmallSystemConfig extends Config(
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithDefaultSerialTL ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUART ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
new chipyard.RocketConfig)