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Merge remote-tracking branch 'origin/dev' into dev-sha3

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This commit is contained in:
Colin Schmidt
2019-09-01 07:20:50 -07:00
parent 8e343dee04 ab888d32a7
commit 5790bbc21b
34 changed files with 816 additions and 544 deletions
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64
.circleci/config.yml
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@@ -117,35 +117,6 @@ jobs:
key: example-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-boomexample:
docker:
- image: riscvboom/riscvboom-images:0.0.10
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
- add_ssh_keys:
fingerprints:
- "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
- run:
name: Building the boomexample subproject using Verilator
command: .circleci/do-rtl-build.sh boomexample
no_output_timeout: 120m
- save_cache:
key: boomexample-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-boomrocketexample:
docker:
- image: riscvboom/riscvboom-images:0.0.10
@@ -170,7 +141,7 @@ jobs:
- run:
name: Building the boomrocketexample subproject using Verilator
command: .circleci/do-rtl-build.sh boomrocketexample
no_output_timeout: 120m
no_output_timeout: 240m
- save_cache:
key: boomrocketexample-{{ .Branch }}-{{ .Revision }}
paths:
@@ -315,30 +286,6 @@ jobs:
- run:
name: Run example tests
command: .circleci/run-tests.sh example
boomexample-run-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.10
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- boomexample-{{ .Branch }}-{{ .Revision }}
- restore_cache:
keys:
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
- run:
name: Run boomexample tests
command: .circleci/run-tests.sh boomexample
boomrocketexample-run-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.10
@@ -468,11 +415,6 @@ workflows:
- install-riscv-toolchain
- install-verilator
- prepare-boomexample:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-boomrocketexample:
requires:
- install-riscv-toolchain
@@ -505,10 +447,6 @@ workflows:
requires:
- prepare-example
- boomexample-run-tests:
requires:
- prepare-boomexample
- boomrocketexample-run-tests:
requires:
- prepare-boomrocketexample

7
.circleci/defaults.sh
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@@ -36,9 +36,8 @@ LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator
# key value store to get the build strings
declare -A mapping
mapping["example"]="SUB_PROJECT=example"
mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig"
mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig"
mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=LargeBoomAndRocketConfig"
mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha"

11
build.sbt
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@@ -106,10 +106,15 @@ lazy val testchipip = (project in file("generators/testchipip"))
.settings(commonSettings)
lazy val example = conditionalDependsOn(project in file("generators/example"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, rocc_template)
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3)
.settings(commonSettings)
lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
.dependsOn(rocketchip, sifive_cache)
.settings(commonSettings)
lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
.dependsOn(rocketchip, boom)
.settings(commonSettings)
lazy val icenet = (project in file("generators/icenet"))
@@ -124,7 +129,7 @@ lazy val boom = (project in file("generators/boom"))
.dependsOn(rocketchip)
.settings(commonSettings)
lazy val rocc_template = (project in file("generators/rocc-template"))
lazy val sha3 = (project in file("generators/sha3"))
.dependsOn(rocketchip, `chisel-testers`)
.settings(commonSettings)
@@ -169,7 +174,7 @@ lazy val midas = ProjectRef(firesimDir, "midas")
lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
lazy val firechip = (project in file("generators/firechip"))
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.settings(
commonSettings,
testGrouping in Test := isolateAllTests( (definedTests in Test).value )

9
common.mk
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@@ -6,11 +6,10 @@ SHELL=/bin/bash
#########################################################################################
# variables to get all *.scala files
#########################################################################################
lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null)
lookup_scala_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.scala" -print 2> /dev/null)
PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache rocc-template example) \
$(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils)
SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala))
SOURCE_DIRS=$(addprefix $(base_dir)/,generators sims/firesim/sim)
SCALA_SOURCES=$(call lookup_scala_srcs,$(SOURCE_DIRS))
#########################################################################################
# rocket and testchipip classes
@@ -68,7 +67,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
# remove duplicate files in blackbox/simfiles
########################################################################################
$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
awk '{print $1;}' $^ | sort -u > $@
awk '{print $1;}' $^ | sort -u | grep -v '.*\.h' > $@
#########################################################################################
# helper rule to just make verilog files

6
docs/Advanced-Usage/DTM-Debugging.rst
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@@ -16,12 +16,12 @@ This involves specifying the SoC top-level to add a DTM as well as configuring t
.. code-block:: scala
class DTMBoomConfig extends Config(
new WithDTMBoomRocketTop ++
new WithDTMTop ++
new WithBootROM ++
new WithJtagDTM ++
new boom.common.SmallBoomConfig)
In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM.
In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM.
The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
The rest of the mixins specify the rest of the system (cores, accelerators, etc).
@@ -36,7 +36,7 @@ After creating the config, call the ``make`` command like the following:
# or
cd sims/vcs
make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM
make CONFIG=DTMBoomConfig TOP=TopWithDTM MODEL=TestHarnessWithDTM
In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!

6
docs/Chipyard-Basics/Running-A-Simulation.rst
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@@ -58,12 +58,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use:
make SUB_PROJECT=example
Alternatively, if we would like to simulate a simple BOOM-based example system we can use:
.. code-block:: shell
make SUB_PROJECT=exampleboom
Once the simulator has been constructed, we would like to run RISC-V programs on it.
In the simulation directory, we will find an executable file called ``<...>-<package>-<config>``.
We run this executable with our target RISC-V program as a command line argument in one of two ways.

9
docs/Customization/Adding-An-Accelerator.rst
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@@ -61,15 +61,6 @@ the ``example`` project, change the final line in build.sbt to the following.
lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject)
Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the Chipyard top level.
This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files.
.. code-block:: shell
PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache example yourproject) \
$(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils)
MMIO Peripheral
------------------

16
docs/Customization/Heterogeneous-SoCs.rst
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@@ -15,18 +15,18 @@ The following example shows a dual core BOOM with a single core Rocket.
.. code-block:: scala
class DualBoomAndOneRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new boom.system.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.common.LargeBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively.
However, for BOOM, an extra mixin called ``DefaultBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
However, for BOOM, an extra mixin called ``LargeBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
This mixin applies to all BOOM cores in the system and changes the parameters for each.
Great! Now you have a heterogeneous setup with BOOMs and Rockets.
@@ -62,7 +62,7 @@ Then you could use this new mixin like the following.
.. code-block:: scala
class SixCoreConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new WithHeterCoresSetup ++
new freechips.rocketchip.system.BaseConfig)
@@ -78,12 +78,12 @@ An example of adding a Hwacha to all tiles in the system is below.
.. code-block:: scala
class DualBoomAndRocketWithHwachasConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new hwacha.DefaultHwachaConfig ++
new boom.system.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.common.LargeBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
@@ -103,14 +103,14 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a
.. code-block:: scala
class DualBoomAndOneHwachaRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new WithMultiRoCC ++
new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
new boom.system.WithRenumberHarts(rocketFirst = true) ++
new hwacha.DefaultHwachaConfig ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.common.LargeBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++

12
docs/Simulation/Software-RTL-Simulators.rst
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@@ -12,16 +12,16 @@ The Chipyard framework can download, build, and execute simulations using Verila
To run a simulation using Verilator, perform the following steps:
To compile the example design, run ``make`` in the ``sims/verilator`` directory.
This will elaborate the ``DefaultRocketConfig`` in the example project.
This will elaborate the ``RocketConfig`` in the example project.
An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
An executable called ``simulator-example-RocketConfig`` will be produced.
This executable is a simulator that has been compiled based on the design that was built.
You can then use this executable to run any compatible RV64 code.
For instance, to run one of the riscv-tools assembly tests.
.. code-block:: shell
./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
If you later create your own project, you can use environment variables to build an alternate configuration.
@@ -50,16 +50,16 @@ To run a simulation using VCS, perform the following steps:
Make sure that the VCS simulator is on your ``PATH``.
To compile the example design, run make in the ``sims/vcs`` directory.
This will elaborate the ``DefaultRocketConfig`` in the example project.
This will elaborate the ``RocketConfig`` in the example project.
An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
An executable called ``simulator-example-RocketConfig`` will be produced.
This executable is a simulator that has been compiled based on the design that was built.
You can then use this executable to run any compatible RV64 code.
For instance, to run one of the riscv-tools assembly tests.
.. code-block:: shell
./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
If you later create your own project, you can use environment variables to build an alternate configuration.

2
generators/boom

Submodule generators/boom updated: 4e9d496d36...7b68d748b6

99
generators/example/src/main/scala/BoomConfigs.scala
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@@ -3,88 +3,57 @@ package example
import chisel3._
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.subsystem.{WithJtagDTM}
import boom.common._
// ---------------------
// BOOM Configs
// ---------------------
class SmallBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.SmallBoomConfig)
new WithTop ++ // use normal top
new WithBootROM ++ // use testchipip bootrom
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache
new boom.common.WithSmallBooms ++ // 1-wide BOOM
new boom.common.WithNBoomCores(1) ++ // single-core
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class MediumBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new boom.common.MediumBoomConfig)
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithMediumBooms ++ // 2-wide BOOM
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class LargeBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new boom.common.LargeBoomConfig)
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithLargeBooms ++ // 3-wide BOOM
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class MegaBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new boom.common.MegaBoomConfig)
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithMegaBooms ++ // 4-wide BOOM
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class jtagSmallBoomConfig extends Config(
new WithDTMBoomRocketTop ++
class DualSmallBoomConfig extends Config(
new WithTop ++
new WithBootROM ++
new WithJtagDTM ++
new boom.common.SmallBoomConfig)
class jtagMediumBoomConfig extends Config(
new WithDTMBoomRocketTop ++
new WithBootROM ++
new WithJtagDTM ++
new boom.common.MediumBoomConfig)
class jtagLargeBoomConfig extends Config(
new WithDTMBoomRocketTop ++
new WithBootROM ++
new WithJtagDTM ++
new boom.common.LargeBoomConfig)
class jtagMegaBoomConfig extends Config(
new WithDTMBoomRocketTop ++
new WithBootROM ++
new WithJtagDTM ++
new boom.common.MegaBoomConfig)
class SmallDualBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.SmallDualBoomConfig)
class TracedSmallBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.TracedSmallBoomConfig)
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(2) ++ // dual-core
new freechips.rocketchip.system.BaseConfig)
class SmallRV32UnifiedBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithTop ++
new WithBootROM ++
new boom.common.SmallRV32UnifiedBoomConfig)
// --------------------------
// BOOM + Rocket Configs
// --------------------------
class SmallBoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.SmallBoomAndRocketConfig)
class MediumBoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.MediumBoomAndRocketConfig)
class DualMediumBoomAndDualRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.DualMediumBoomAndDualRocketConfig)
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithoutBoomFPU ++ // no floating point
new boom.common.WithUnifiedMemIntIQs ++ // use unified mem+int issue queues
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig)

44
generators/example/src/main/scala/ConfigMixins.scala
View File

@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC}
import boom.system.{BoomTilesKey}
import boom.common.{BoomTilesKey}
import testchipip._
@@ -52,43 +52,43 @@ class WithGPIO extends Config((site, here, up) => {
/**
* Class to specify a "plain" top level BOOM and/or Rocket system
*/
class WithNormalBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new BoomRocketTop()(p)).module)
class WithTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new Top()(p)).module)
}
})
/**
* Class to specify a top level BOOM and/or Rocket system with DTM
*/
class WithDTMBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new BoomRocketTopWithDTM()(p)).module)
class WithDTMTop extends Config((site, here, up) => {
case BuildTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new TopWithDTM()(p)).module)
}
})
/**
* Class to specify a top level BOOM and/or Rocket system with PWM
*/
class WithPWMBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module)
class WithPWMTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new TopWithPWMTL()(p)).module)
})
/**
* Class to specify a top level BOOM and/or Rocket system with a PWM AXI4
*/
class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module)
class WithPWMAXI4Top extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new TopWithPWMAXI4()(p)).module)
})
/**
* Class to specify a top level BOOM and/or Rocket system with a block device
*/
class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
class WithBlockDeviceModelTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
top.connectBlockDeviceModel()
top
}
@@ -97,9 +97,9 @@ class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
/**
* Class to specify a top level BOOM and/or Rocket system with a simulator block device
*/
class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
class WithSimBlockDeviceTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
top.connectSimBlockDevice(clock, reset)
top
}
@@ -108,9 +108,9 @@ class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
/**
* Class to specify a top level BOOM and/or Rocket system with GPIO
*/
class WithGPIOBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module)
class WithGPIOTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new TopWithGPIO()(p)).module)
for (gpio <- top.gpio) {
for (pin <- gpio.pins) {
pin.i.ival := false.B

270
generators/example/src/main/scala/Configs.scala
View File

@@ -1,270 +0,0 @@
package example
import chisel3._
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache}
import testchipip._
// --------------
// Rocket Configs
// --------------
class BaseRocketConfig extends Config(
new WithBootROM ++
new freechips.rocketchip.system.DefaultConfig)
class DefaultRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new BaseRocketConfig)
class HwachaConfig extends Config(
new hwacha.DefaultHwachaConfig ++
new DefaultRocketConfig)
class RoccRocketConfig extends Config(
new WithRoccExample ++
new DefaultRocketConfig)
class Sha3RocketConfig extends Config(
new sha3.WithSha3Accel ++
new DefaultRocketConfig)
class PWMRocketConfig extends Config(
new WithPWMBoomRocketTop ++
new BaseRocketConfig)
class PWMAXI4RocketConfig extends Config(
new WithPWMAXI4BoomRocketTop ++
new BaseRocketConfig)
class SimBlockDeviceRocketConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomRocketTop ++
new BaseRocketConfig)
class BlockDeviceModelRocketConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomRocketTop ++
new BaseRocketConfig)
class GPIORocketConfig extends Config(
new WithGPIO ++
new WithGPIOBoomRocketTop ++
new BaseRocketConfig)
class DualCoreRocketConfig extends Config(
new WithNBigCores(2) ++
new DefaultRocketConfig)
class RV32RocketConfig extends Config(
new WithRV32 ++
new DefaultRocketConfig)
class GB1MemoryConfig extends Config(
new WithExtMemSize((1<<30) * 1L) ++
new DefaultRocketConfig)
class RocketL2Config extends Config(
new WithInclusiveCache ++
new DefaultRocketConfig)
class HwachaL2Config extends Config(
new hwacha.DefaultHwachaConfig ++
new WithInclusiveCache ++
new DefaultRocketConfig)
// ------------
// BOOM Configs
// ------------
class BaseBoomConfig extends Config(
new WithBootROM ++
new boom.common.LargeBoomConfig)
class SmallBaseBoomConfig extends Config(
new WithBootROM ++
new boom.common.SmallBoomConfig)
class DefaultBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new BaseBoomConfig)
class SmallDefaultBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new SmallBaseBoomConfig)
class HwachaBoomConfig extends Config(
new hwacha.DefaultHwachaConfig ++
new DefaultBoomConfig)
class RoccBoomConfig extends Config(
new WithRoccExample ++
new DefaultBoomConfig)
class PWMBoomConfig extends Config(
new WithPWMBoomRocketTop ++
new BaseBoomConfig)
class PWMAXI4BoomConfig extends Config(
new WithPWMAXI4BoomRocketTop ++
new BaseBoomConfig)
class SimBlockDeviceBoomConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomRocketTop ++
new BaseBoomConfig)
class BlockDeviceModelBoomConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomRocketTop ++
new BaseBoomConfig)
class GPIOBoomConfig extends Config(
new WithGPIO ++
new WithGPIOBoomRocketTop ++
new BaseBoomConfig)
/**
* Slightly different looking configs since we need to override
* the `WithNBoomCores` with the DefaultBoomConfig params
*/
class DualCoreBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.WithRVC ++
new boom.common.WithLargeBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.system.BaseConfig)
class DualCoreSmallBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.WithRVC ++
new boom.common.WithSmallBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.system.BaseConfig)
class RV32UnifiedBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.SmallRV32UnifiedBoomConfig)
class BoomL2Config extends Config(
new WithInclusiveCache ++
new SmallDefaultBoomConfig)
// ---------------------
// BOOM and Rocket Configs
// ---------------------
class BaseBoomAndRocketConfig extends Config(
new WithBootROM ++
new boom.common.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.WithLargeBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class SmallBaseBoomAndRocketConfig extends Config(
new WithBootROM ++
new boom.common.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.WithSmallBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DefaultBoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new BaseBoomAndRocketConfig)
class SmallDefaultBoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new SmallBaseBoomAndRocketConfig)
class HwachaBoomAndRocketConfig extends Config(
new hwacha.DefaultHwachaConfig ++
new DefaultBoomAndRocketConfig)
class RoccBoomAndRocketConfig extends Config(
new WithRoccExample ++
new DefaultBoomAndRocketConfig)
class PWMBoomAndRocketConfig extends Config(
new WithPWMBoomRocketTop ++
new BaseBoomAndRocketConfig)
class PWMAXI4BoomAndRocketConfig extends Config(
new WithPWMAXI4BoomRocketTop ++
new BaseBoomAndRocketConfig)
class SimBlockDeviceBoomAndRocketConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomRocketTop ++
new BaseBoomAndRocketConfig)
class BlockDeviceModelBoomAndRocketConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomRocketTop ++
new BaseBoomAndRocketConfig)
class GPIOBoomAndRocketConfig extends Config(
new WithGPIO ++
new WithGPIOBoomRocketTop ++
new BaseBoomAndRocketConfig)
class DualCoreBoomAndOneRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.WithLargeBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualBoomAndOneHwachaRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new WithMultiRoCC ++
new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
new boom.common.WithRenumberHarts(rocketFirst = true) ++
new hwacha.DefaultHwachaConfig ++
new boom.common.WithRVC ++
new boom.common.WithLargeBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class RV32BoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.WithRenumberHarts ++
new boom.common.WithBoomRV32 ++
new boom.common.WithRVC ++
new boom.common.WithLargeBooms ++
new boom.common.BaseBoomConfig ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithRV32 ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualCoreRocketL2Config extends Config(
new WithInclusiveCache ++
new DualCoreRocketConfig)

1
generators/example/src/main/scala/Generator.scala
View File

@@ -4,6 +4,7 @@ import chisel3._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import utilities.TestSuiteHelper
object Generator extends GeneratorApp {
// add unique test suites

94
generators/example/src/main/scala/HeteroConfigs.scala Normal file
View File

@@ -0,0 +1,94 @@
package example
import chisel3._
import freechips.rocketchip.config.{Config}
// ---------------------
// Heterogenous Configs
// ---------------------
class LargeBoomAndRocketConfig extends Config(
new WithTop ++ // default top
new WithBootROM ++ // default bootrom
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2
new boom.common.WithRenumberHarts ++ // avoid hartid overlap
new boom.common.WithLargeBooms ++ // 3-wide boom
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class SmallBoomAndRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithRenumberHarts ++
new boom.common.WithSmallBooms ++ // 1-wide boom
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class RoccLargeBoomAndRoccRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithRoccExample ++ // add example rocc accelerator to all harts
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualLargeBoomAndRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(2) ++ // 2-boom cores
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualLargeBoomAndHwachaRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new WithMultiRoCC ++ // support heterogeneous rocc
new WithMultiRoCCHwacha(2) ++ // put hwacha on hart-2 (rocket)
new boom.common.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class LargeBoomAndRV32RocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithRV32 ++ // use 32-bit rocket
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualLargeBoomAndDualRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new boom.common.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
new freechips.rocketchip.system.BaseConfig)

109
generators/example/src/main/scala/RocketConfigs.scala Normal file
View File

@@ -0,0 +1,109 @@
package example
import chisel3._
import freechips.rocketchip.config.{Config}
// --------------
// Rocket Configs
// --------------
class RocketConfig extends Config(
new WithTop ++ // use default top
new WithBootROM ++ // use default bootrom
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class HwachaRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class RoccRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class jtagRocketConfig extends Config(
new WithDTMTop ++ // use top with dtm
new freechips.rocketchip.subsystem.WithJtagDTM ++ // add jtag/DTM module to coreplex
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class PWMRocketConfig extends Config(
new WithPWMTop ++ // use top with tilelink-controlled PWM
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class PWMRAXI4ocketConfig extends Config(
new WithPWMAXI4Top ++ // use top with axi4-controlled PWM
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class SimBlockDeviceRocketConfig extends Config(
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
new WithSimBlockDeviceTop ++ // use top with block-device IOs and connect to simblockdevice
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class BlockDeviceModelRocketConfig extends Config(
new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
new WithBlockDeviceModelTop ++ // use top with block-device IOs and connect to a blockdevicemodel
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class GPIORocketConfig extends Config(
new WithGPIO ++ // add GPIOs to the peripherybus
new WithGPIOTop ++ // use top with GPIOs
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualCoreRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles)
new freechips.rocketchip.system.BaseConfig)
class RV32RocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class GB1MemoryRocketConfig extends Config(
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 2GB simulated external memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class Sha3RocketConfig extends Config(
new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
new WithTop ++
new WithBootROM ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)

8
generators/example/src/main/scala/TestHarness.scala
View File

@@ -14,8 +14,8 @@ import freechips.rocketchip.devices.debug.{Debug}
// BOOM and/or Rocket Test Harness
// -------------------------------
case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]]
case object BuildTop extends Field[(Clock, Bool, Parameters) => TopModule[Top]]
case object BuildTopWithDTM extends Field[(Clock, Bool, Parameters) => TopWithDTMModule[TopWithDTM]]
/**
* Test harness using TSI to bringup the system
@@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
// force Chisel to rename module
override def desiredName = "TestHarness"
val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
val dut = p(BuildTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.connectSimAXIMem()
@@ -63,7 +63,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
// force Chisel to rename module
override def desiredName = "TestHarness"
val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p)
val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
dut.reset := reset.asBool | dut.debug.ndreset
dut.connectSimAXIMem()

42
generators/example/src/main/scala/Top.scala
View File

@@ -10,69 +10,71 @@ import freechips.rocketchip.util.DontTouch
import testchipip._
import utilities.{System, SystemModule}
import sifive.blocks.devices.gpio._
// ------------------------------------
// BOOM and/or Rocket Top Level Systems
// ------------------------------------
class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem
class Top(implicit p: Parameters) extends System
with HasNoDebug
with HasPeripherySerial {
override lazy val module = new BoomRocketTopModule(this)
override lazy val module = new TopModule(this)
}
class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.BoomRocketSystemModule(l)
class TopModule[+L <: Top](l: L) extends SystemModule(l)
with HasNoDebugModuleImp
with HasPeripherySerialModuleImp
with DontTouch
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop
class TopWithPWMTL(implicit p: Parameters) extends Top
with HasPeripheryPWMTL {
override lazy val module = new BoomRocketTopWithPWMTLModule(this)
override lazy val module = new TopWithPWMTLModule(this)
}
class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l)
class TopWithPWMTLModule(l: TopWithPWMTL) extends TopModule(l)
with HasPeripheryPWMTLModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop
class TopWithPWMAXI4(implicit p: Parameters) extends Top
with HasPeripheryPWMAXI4 {
override lazy val module = new BoomRocketTopWithPWMAXI4Module(this)
override lazy val module = new TopWithPWMAXI4Module(this)
}
class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l)
class TopWithPWMAXI4Module(l: TopWithPWMAXI4) extends TopModule(l)
with HasPeripheryPWMAXI4ModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop
class TopWithBlockDevice(implicit p: Parameters) extends Top
with HasPeripheryBlockDevice {
override lazy val module = new BoomRocketTopWithBlockDeviceModule(this)
override lazy val module = new TopWithBlockDeviceModule(this)
}
class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l)
class TopWithBlockDeviceModule(l: TopWithBlockDevice) extends TopModule(l)
with HasPeripheryBlockDeviceModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
with HasPeripheryGPIO {
override lazy val module = new BoomRocketTopWithGPIOModule(this)
class TopWithGPIO(implicit p: Parameters) extends Top
with HasPeripheryGPIO {
override lazy val module = new TopWithGPIOModule(this)
}
class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
extends BoomRocketTopModule(l)
class TopWithGPIOModule(l: TopWithGPIO)
extends TopModule(l)
with HasPeripheryGPIOModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem
class TopWithDTM(implicit p: Parameters) extends System
{
override lazy val module = new BoomRocketTopWithDTMModule(this)
override lazy val module = new TopWithDTMModule(this)
}
class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l)
class TopWithDTMModule[+L <: TopWithDTM](l: L) extends SystemModule(l)

42
generators/firechip/src/main/scala/Generator.scala
View File

@@ -16,10 +16,10 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.subsystem.RocketTilesKey
import freechips.rocketchip.tile.XLen
import boom.system.{BoomTilesKey, BoomTestSuites}
import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
import utilities.TestSuiteHelper
trait HasTestSuites {
val rv64RegrTestNames = collection.mutable.LinkedHashSet(
"rv64ud-v-fcvt",
@@ -27,8 +27,8 @@ trait HasTestSuites {
"rv64ud-v-fadd",
"rv64uf-v-fadd",
"rv64um-v-mul",
// "rv64mi-p-breakpoint", // Not implemented in BOOM
// "rv64uc-v-rvc", // Not implemented in BOOM
"rv64mi-p-breakpoint",
"rv64uc-v-rvc",
"rv64ud-v-structural",
"rv64si-p-wfi",
"rv64um-v-divw",
@@ -58,38 +58,8 @@ trait HasTestSuites {
"rv32ui-p-sll")
def addTestSuites(targetName: String, params: Parameters) {
val coreParams =
if (params(RocketTilesKey).nonEmpty) {
params(RocketTilesKey).head.core
} else {
params(BoomTilesKey).head.core
}
val xlen = params(XLen)
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
TestSuiteHelper.addRocketTestSuites(params)
TestSuiteHelper.addBoomTestSuites(params)
TestGeneration.addSuite(FastBlockdevTests)
TestGeneration.addSuite(SlowBlockdevTests)
if (!targetName.contains("NoNIC"))

78
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -4,14 +4,18 @@ import java.io.File
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.groundtest.TraceGenParams
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.debug.DebugModuleParams
import boom.system.BoomTilesKey
import boom.common.BoomTilesKey
import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import scala.math.{min, max}
import tracegen.TraceGenKey
import icenet._
class WithBootROM extends Config((site, here, up) => {
@@ -136,8 +140,10 @@ class FireSimBoomConfig extends Config(
new WithBlockDevice ++
new WithBoomL2TLBs(1024) ++
new WithoutClockGating ++
// Using a small config because it has 64-bit system bus, and compiles quickly
new boom.system.SmallBoomConfig)
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig
)
// A safer implementation than the one in BOOM in that it
// duplicates whatever BOOMTileKey.head is present N times. This prevents
@@ -203,3 +209,69 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipOctaCoreConfig)
class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
extends Config((site, here, up) => {
case TraceGenKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val nSets = dcp.nSets
val nWays = dcp.nWays
val blockOffset = site(SystemBusKey).blockOffset
val nBeats = min(2, site(SystemBusKey).blockBeats)
val beatBytes = site(SystemBusKey).beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = site(ExtMem).get.master.base,
numGens = params.size)
}
case MaxHartIdBits => log2Up(params.size)
})
class FireSimTraceGenConfig extends Config(
new WithTraceGen(
List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new FireSimRocketChipConfig)
class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
extends Config((site, here, up) => {
case TraceGenKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val sbp = site(SystemBusKey)
val l2p = site(InclusiveCacheKey)
val nSets = max(l2p.sets, dcp.nSets)
val nWays = max(l2p.ways, dcp.nWays)
val nBanks = site(BankedL2Key).nBanks
val blockOffset = sbp.blockOffset
val nBeats = min(2, sbp.blockBeats)
val beatBytes = sbp.beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = site(ExtMem).get.master.base,
numGens = params.size)
}
case MaxHartIdBits => log2Up(params.size)
})
class FireSimTraceGenL2Config extends Config(
new WithL2TraceGen(
List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new WithInclusiveCache(
nBanks = 4,
capacityKB = 1024,
outerLatencyCycles = 50) ++
new FireSimRocketChipConfig)

1
generators/firechip/src/main/scala/TargetMixins.scala
View File

@@ -103,4 +103,3 @@ trait HasTraceIOImp extends LazyModuleImp {
trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
}

22
generators/firechip/src/main/scala/Targets.scala
View File

@@ -11,10 +11,11 @@ import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.amba.axi4.AXI4Bundle
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.LazyModule
import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp}
import utilities.{Subsystem, SubsystemModuleImp}
import icenet._
import testchipip._
import testchipip.SerialAdapter.SERIAL_IF_WIDTH
import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
import sifive.blocks.devices.uart._
import midas.models.AXI4BundleWithEdge
import java.io.File
@@ -80,7 +81,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
with HasTraceIOImp
class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
class FireBoom(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM
@@ -94,7 +95,7 @@ class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
override lazy val module = new FireBoomModuleImp(this)
}
class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l)
class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
@@ -106,7 +107,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI
with HasTraceIOImp
with ExcludeInvalidBoomAssertions
class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM
@@ -119,7 +120,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
override lazy val module = new FireBoomNoNICModuleImp(this)
}
class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l)
class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
@@ -174,3 +175,14 @@ class FireSimSupernode(implicit p: Parameters) extends Module {
} }
}
class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
with HasHierarchicalBusTopology
with HasTraceGenTiles
with CanHaveFASEDOptimizedMasterAXI4MemPort {
override lazy val module = new FireSimTraceGenModuleImp(this)
}
class FireSimTraceGenModuleImp(outer: FireSimTraceGen)
extends BaseSubsystemModuleImp(outer)
with HasTraceGenTilesModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp

2
generators/icenet

Submodule generators/icenet updated: bba264d68d...baa40ed85d

2
generators/testchipip

Submodule generators/testchipip updated: 85db33c398...aa13f6ccc1

76
generators/tracegen/src/main/scala/Configs.scala Normal file
View File

@@ -0,0 +1,76 @@
package tracegen
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.config.{Config, Parameters}
import freechips.rocketchip.groundtest.{TraceGenParams}
import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey}
import freechips.rocketchip.system.BaseConfig
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
import scala.math.{max, min}
class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
extends Config((site, here, up) => {
case TraceGenKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val nSets = dcp.nSets
val nWays = dcp.nWays
val blockOffset = site(SystemBusKey).blockOffset
val nBeats = min(2, site(SystemBusKey).blockBeats)
val beatBytes = site(SystemBusKey).beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = site(ExtMem).get.master.base,
numGens = params.size)
}
case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
})
class TraceGenConfig extends Config(
new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
new BaseConfig)
class NonBlockingTraceGenConfig extends Config(
new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new BaseConfig)
class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
extends Config((site, here, up) => {
case TraceGenKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val sbp = site(SystemBusKey)
val l2p = site(InclusiveCacheKey)
val nSets = max(l2p.sets, dcp.nSets)
val nWays = max(l2p.ways, dcp.nWays)
val blockOffset = sbp.blockOffset
val nBeats = min(2, sbp.blockBeats)
val beatBytes = sbp.beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = site(ExtMem).get.master.base,
numGens = params.size)
}
case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
})
class NonBlockingTraceGenL2Config extends Config(
new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new WithInclusiveCache ++
new BaseConfig)

43
generators/tracegen/src/main/scala/System.scala Normal file
View File

@@ -0,0 +1,43 @@
package tracegen
import chisel3._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams}
import freechips.rocketchip.subsystem._
case object TraceGenKey extends Field[Seq[TraceGenParams]]
trait HasTraceGenTiles { this: BaseSubsystem =>
val tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
LazyModule(new TraceGenTile(i, params, p))
}
tiles.foreach { t =>
sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode }
}
}
trait HasTraceGenTilesModuleImp extends LazyModuleImp {
val outer: HasTraceGenTiles
val success = IO(Output(Bool()))
outer.tiles.zipWithIndex.map { case(t, i) =>
t.module.constants.hartid := i.U
}
val status = DebugCombiner(outer.tiles.map(_.module.status))
success := status.finished
}
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with HasTraceGenTiles
with HasHierarchicalBusTopology
with CanHaveMasterAXI4MemPort {
override lazy val module = new TraceGenSystemModuleImp(this)
}
class TraceGenSystemModuleImp(outer: TraceGenSystem)
extends BaseSubsystemModuleImp(outer)
with HasTraceGenTilesModuleImp
with CanHaveMasterAXI4MemPortModuleImp

27
generators/tracegen/src/main/scala/TestHarness.scala Normal file
View File

@@ -0,0 +1,27 @@
package tracegen
import chisel3._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.util.GeneratorApp
class TestHarness(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val success = Output(Bool())
})
val dut = Module(LazyModule(new TraceGenSystem).module)
io.success := dut.success
dut.connectSimAXIMem()
}
object Generator extends GeneratorApp {
// specify the name that the generator outputs files as
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
// generate files
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}

53
generators/tracegen/src/main/scala/Tile.scala Normal file
View File

@@ -0,0 +1,53 @@
package tracegen
import chisel3._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing}
import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus}
import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF}
import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate}
import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode}
import freechips.rocketchip.interrupts._
class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters)
extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) {
val dcache = params.dcache.map { dc => LazyModule(
if (dc.nMSHRs == 0) new DCache(hartId, crossing)
else new NonBlockingDCache(hartId))
}.get
val intInwardNode: IntInwardNode = IntIdentityNode()
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val ceaseNode: IntOutwardNode = IntIdentityNode()
val haltNode: IntOutwardNode = IntIdentityNode()
val wfiNode: IntOutwardNode = IntIdentityNode()
val masterNode = visibilityNode
masterNode := dcache.node
override lazy val module = new TraceGenTileModuleImp(this)
}
class TraceGenTileModuleImp(outer: TraceGenTile)
extends BaseTileModuleImp(outer) {
val status = IO(new GroundTestStatus)
val halt_and_catch_fire = None
val ptw = Module(new DummyPTW(1))
ptw.io.requestors.head <> outer.dcache.module.io.ptw
val tracegen = Module(new TraceGenerator(outer.params))
tracegen.io.hartid := constants.hartid
val dcacheIF = Module(new SimpleHellaCacheIF())
dcacheIF.io.requestor <> tracegen.io.mem
outer.dcache.module.io.cpu <> dcacheIF.io.cache
status.finished := tracegen.io.finished
status.timeout.valid := tracegen.io.timeout
status.timeout.bits := 0.U
status.error.valid := false.B
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
}

108
generators/utilities/src/main/scala/Subsystem.scala Normal file
View File

@@ -0,0 +1,108 @@
//******************************************************************************
// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package utilities
import chisel3._
import chisel3.internal.sourceinfo.{SourceInfo}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey}
trait HasBoomAndRocketTiles extends HasTiles
with CanHavePeripheryPLIC
with CanHavePeripheryCLINT
with HasPeripheryDebug
{ this: BaseSubsystem =>
val module: HasBoomAndRocketTilesModuleImp
protected val rocketTileParams = p(RocketTilesKey)
protected val boomTileParams = p(BoomTilesKey)
// crossing can either be per tile or global (aka only 1 crossing specified)
private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
// Make a tile and wire its nodes into the system,
// according to the specified type of clock crossing.
// Note that we also inject new nodes into the tile itself,
// also based on the crossing type.
val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
connectMasterPortsToSBus(rocket, crossing)
connectSlavePortsToCBus(rocket, crossing)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree)
rocket
}
val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
connectMasterPortsToSBus(boom, crossing)
connectSlavePortsToCBus(boom, crossing)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree)
boom
}
// combine tiles and connect interrupts based on the order of harts
val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map {
tile => {
connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
tile
}
}
def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
(boomTiles map { t => t.module.core.coreMonitorBundle}).toList
}
trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
with HasPeripheryDebugModuleImp
{
val outer: HasBoomAndRocketTiles
}
class Subsystem(implicit p: Parameters) extends BaseSubsystem
with HasBoomAndRocketTiles
{
val tiles = boomAndRocketTiles
override lazy val module = new SubsystemModuleImp(this)
def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
}
class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasResetVectorWire
with HasBoomAndRocketTilesModuleImp
{
tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.hartid := i.U
wire.reset_vector := global_reset_vector
}
// create file with boom params
ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
}

45
generators/utilities/src/main/scala/System.scala Normal file
View File

@@ -0,0 +1,45 @@
//******************************************************************************
// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package utilities
import chisel3._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util.{DontTouch}
// ---------------------------------------------------------------------
// Base system that uses the debug test module (dtm) to bringup the core
// ---------------------------------------------------------------------
/**
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class System(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort
with CanHaveSlaveAXI4Port
with HasPeripheryBootROM
{
override lazy val module = new SystemModule(this)
}
/**
* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MMIOPortModuleImp
with CanHaveSlaveAXI4PortModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

4
generators/example/src/main/scala/TestSuites.scala → generators/utilities/src/main/scala/TestSuites.scala
View File

@@ -1,4 +1,4 @@
package example
package utilities
import scala.collection.mutable.{LinkedHashSet}
@@ -8,7 +8,7 @@ import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import boom.system.{BoomTilesKey}
import boom.common.{BoomTilesKey}
/**
* A set of pre-chosen regression tests

23
scripts/check-tracegen.sh Executable file
View File

@@ -0,0 +1,23 @@
#!/bin/bash
set -e
SCRIPT_DIR=$(dirname $0)
AXE_DIR=$(realpath ${SCRIPT_DIR}/../../axe)
ROCKET_DIR=$(realpath ${SCRIPT_DIR}/../generators/rocket-chip)
TO_AXE=${ROCKET_DIR}/scripts/toaxe.py
AXE=${AXE_DIR}/src/axe
AXE_SHRINK=${AXE_DIR}/src/axe-shrink.py
PATH=$PATH:${AXE_DIR}/src
grep '.*:.*#.*@' $1 > /tmp/clean-trace.txt
$TO_AXE /tmp/clean-trace.txt > /tmp/trace.axe
result=$($AXE check wmo /tmp/trace.axe)
if [ $result != "OK" ]; then
$AXE_SHRINK wmo /tmp/trace.axe
else
echo "OK"
fi

10
sims/verilator/Makefile
View File

@@ -51,7 +51,7 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv
VERILATOR_CC_OPTS = \
-O3 \
-CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \
-LDFLAGS "$(LDFLAGS)"
VERILATOR_NONCC_OPTS = \
@@ -59,7 +59,8 @@ VERILATOR_NONCC_OPTS = \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\) \
--assert \
--output-split 20000 \
--output-split 10000 \
--output-split-cfuncs 100 \
$(sim_vsrcs) \
-f $(sim_common_files)
@@ -96,11 +97,12 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
#########################################################################################
# invoke make to make verilator sim rules
#########################################################################################
VERILATOR_MAKEFLAGS=-j8
$(sim): $(model_mk)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
$(MAKE) $(VERILATOR_MAKEFLAGS) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
$(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
$(MAKE) $(VERILATOR_MAKEFLAGS) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
#########################################################################################
# create a verilator vpd rule

15
variables.mk
View File

@@ -32,11 +32,22 @@ ifeq ($(SUB_PROJECT),example)
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= $(SBT_PROJECT)
CONFIG ?= DefaultRocketConfig
CONFIG ?= RocketConfig
CONFIG_PACKAGE ?= $(SBT_PROJECT)
GENERATOR_PACKAGE ?= $(SBT_PROJECT)
TB ?= TestDriver
TOP ?= BoomRocketTop
TOP ?= Top
endif
ifeq ($(SUB_PROJECT),tracegen)
SBT_PROJECT ?= tracegen
MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= $(SBT_PROJECT)
CONFIG ?= TraceGenConfig
CONFIG_PACKAGE ?= $(SBT_PROJECT)
GENERATOR_PACKAGE ?= $(SBT_PROJECT)
TB ?= TestDriver
TOP ?= TraceGenSystem
endif
# for Rocket-chip developers
ifeq ($(SUB_PROJECT),rocketchip)